hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
commit10b43754cf299af85bdb1996594ddd54bc517094
authorAnup Patel <anup.patel@wdc.com>
Wed, 11 Nov 2020 09:47:25 +0000 (11 15:17 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 18 Dec 2020 05:56:43 +0000 (17 21:56 -0800)
treea482992e51c545eac99b57d8399a14bc71c03edf
parent75ee62ac606bfc9eb59310b9446df3434bf6e8c2
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB

The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/sifive_u.c