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hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
[qemu/ar7.git] / hw / riscv / sifive_u.c
bloba629416785cb3282ea3ca5a7c3eac13ec43071e7
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 *
19 * This board currently generates devicetree dynamically that indicates at least
20 * two harts and up to five harts.
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms and conditions of the GNU General Public License,
24 * version 2 or later, as published by the Free Software Foundation.
25 *
26 * This program is distributed in the hope it will be useful, but WITHOUT
27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
29 * more details.
30 *
31 * You should have received a copy of the GNU General Public License along with
32 * this program. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35 #include "qemu/osdep.h"
36 #include "qemu/log.h"
37 #include "qemu/error-report.h"
38 #include "qapi/error.h"
39 #include "qapi/visitor.h"
40 #include "hw/boards.h"
41 #include "hw/irq.h"
42 #include "hw/loader.h"
43 #include "hw/sysbus.h"
44 #include "hw/char/serial.h"
45 #include "hw/cpu/cluster.h"
46 #include "hw/misc/unimp.h"
47 #include "target/riscv/cpu.h"
48 #include "hw/riscv/riscv_hart.h"
49 #include "hw/riscv/sifive_u.h"
50 #include "hw/riscv/boot.h"
51 #include "hw/char/sifive_uart.h"
52 #include "hw/intc/sifive_clint.h"
53 #include "hw/intc/sifive_plic.h"
54 #include "chardev/char.h"
55 #include "net/eth.h"
56 #include "sysemu/arch_init.h"
57 #include "sysemu/device_tree.h"
58 #include "sysemu/runstate.h"
59 #include "sysemu/sysemu.h"
60
61 #include <libfdt.h>
62
63 #if defined(TARGET_RISCV32)
64 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
65 #else
66 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
67 #endif
68
69 static const struct MemmapEntry {
70 hwaddr base;
71 hwaddr size;
72 } sifive_u_memmap[] = {
73 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
74 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
75 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
76 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
77 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
78 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
79 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
80 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
81 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
82 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
90 };
91
92 #define OTP_SERIAL 1
93 #define GEM_REVISION 0x10070109
94
95 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
96 uint64_t mem_size, const char *cmdline)
97 {
98 MachineState *ms = MACHINE(qdev_get_machine());
99 void *fdt;
100 int cpu;
101 uint32_t *cells;
102 char *nodename;
103 char ethclk_names[] = "pclk\0hclk";
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
106
107 if (ms->dtb) {
108 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
109 if (!fdt) {
110 error_report("load_device_tree() failed");
111 exit(1);
112 }
113 goto update_bootargs;
114 } else {
115 fdt = s->fdt = create_device_tree(&s->fdt_size);
116 if (!fdt) {
117 error_report("create_device_tree() failed");
118 exit(1);
119 }
120 }
121
122 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
123 qemu_fdt_setprop_string(fdt, "/", "compatible",
124 "sifive,hifive-unleashed-a00");
125 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
126 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
127
128 qemu_fdt_add_subnode(fdt, "/soc");
129 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
130 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
131 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
132 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
133
134 hfclk_phandle = phandle++;
135 nodename = g_strdup_printf("/hfclk");
136 qemu_fdt_add_subnode(fdt, nodename);
137 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
138 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
139 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
140 SIFIVE_U_HFCLK_FREQ);
141 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
142 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
143 g_free(nodename);
144
145 rtcclk_phandle = phandle++;
146 nodename = g_strdup_printf("/rtcclk");
147 qemu_fdt_add_subnode(fdt, nodename);
148 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
149 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
150 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
151 SIFIVE_U_RTCCLK_FREQ);
152 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
153 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
154 g_free(nodename);
155
156 nodename = g_strdup_printf("/memory@%lx",
157 (long)memmap[SIFIVE_U_DEV_DRAM].base);
158 qemu_fdt_add_subnode(fdt, nodename);
159 qemu_fdt_setprop_cells(fdt, nodename, "reg",
160 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
161 mem_size >> 32, mem_size);
162 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
163 g_free(nodename);
164
165 qemu_fdt_add_subnode(fdt, "/cpus");
166 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
167 SIFIVE_CLINT_TIMEBASE_FREQ);
168 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
169 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
170
171 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
172 int cpu_phandle = phandle++;
173 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
174 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
175 char *isa;
176 qemu_fdt_add_subnode(fdt, nodename);
177 /* cpu 0 is the management hart that does not have mmu */
178 if (cpu != 0) {
179 #if defined(TARGET_RISCV32)
180 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
181 #else
182 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
183 #endif
184 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
185 } else {
186 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
187 }
188 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
189 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
190 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
191 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
192 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
193 qemu_fdt_add_subnode(fdt, intc);
194 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
195 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
196 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
197 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
198 g_free(isa);
199 g_free(intc);
200 g_free(nodename);
201 }
202
203 cells = g_new0(uint32_t, ms->smp.cpus * 4);
204 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
205 nodename =
206 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
207 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
208 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
209 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
210 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
211 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
212 g_free(nodename);
213 }
214 nodename = g_strdup_printf("/soc/clint@%lx",
215 (long)memmap[SIFIVE_U_DEV_CLINT].base);
216 qemu_fdt_add_subnode(fdt, nodename);
217 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
218 qemu_fdt_setprop_cells(fdt, nodename, "reg",
219 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
220 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
221 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
222 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
223 g_free(cells);
224 g_free(nodename);
225
226 nodename = g_strdup_printf("/soc/otp@%lx",
227 (long)memmap[SIFIVE_U_DEV_OTP].base);
228 qemu_fdt_add_subnode(fdt, nodename);
229 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
230 qemu_fdt_setprop_cells(fdt, nodename, "reg",
231 0x0, memmap[SIFIVE_U_DEV_OTP].base,
232 0x0, memmap[SIFIVE_U_DEV_OTP].size);
233 qemu_fdt_setprop_string(fdt, nodename, "compatible",
234 "sifive,fu540-c000-otp");
235 g_free(nodename);
236
237 prci_phandle = phandle++;
238 nodename = g_strdup_printf("/soc/clock-controller@%lx",
239 (long)memmap[SIFIVE_U_DEV_PRCI].base);
240 qemu_fdt_add_subnode(fdt, nodename);
241 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
242 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
243 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
244 hfclk_phandle, rtcclk_phandle);
245 qemu_fdt_setprop_cells(fdt, nodename, "reg",
246 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
247 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
248 qemu_fdt_setprop_string(fdt, nodename, "compatible",
249 "sifive,fu540-c000-prci");
250 g_free(nodename);
251
252 plic_phandle = phandle++;
253 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
254 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
255 nodename =
256 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
257 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
258 /* cpu 0 is the management hart that does not have S-mode */
259 if (cpu == 0) {
260 cells[0] = cpu_to_be32(intc_phandle);
261 cells[1] = cpu_to_be32(IRQ_M_EXT);
262 } else {
263 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
264 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
265 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
266 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
267 }
268 g_free(nodename);
269 }
270 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
271 (long)memmap[SIFIVE_U_DEV_PLIC].base);
272 qemu_fdt_add_subnode(fdt, nodename);
273 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
274 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
275 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
276 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
277 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
278 qemu_fdt_setprop_cells(fdt, nodename, "reg",
279 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
280 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
281 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
282 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
283 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
284 g_free(cells);
285 g_free(nodename);
286
287 gpio_phandle = phandle++;
288 nodename = g_strdup_printf("/soc/gpio@%lx",
289 (long)memmap[SIFIVE_U_DEV_GPIO].base);
290 qemu_fdt_add_subnode(fdt, nodename);
291 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
292 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
293 prci_phandle, PRCI_CLK_TLCLK);
294 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
295 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
296 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
297 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
298 qemu_fdt_setprop_cells(fdt, nodename, "reg",
299 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
300 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
301 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
302 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
303 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
304 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
305 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
306 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
307 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
308 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
309 g_free(nodename);
310
311 nodename = g_strdup_printf("/gpio-restart");
312 qemu_fdt_add_subnode(fdt, nodename);
313 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
314 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
315 g_free(nodename);
316
317 nodename = g_strdup_printf("/soc/dma@%lx",
318 (long)memmap[SIFIVE_U_DEV_PDMA].base);
319 qemu_fdt_add_subnode(fdt, nodename);
320 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
321 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
322 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
323 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
324 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
325 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
326 qemu_fdt_setprop_cells(fdt, nodename, "reg",
327 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
328 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
329 qemu_fdt_setprop_string(fdt, nodename, "compatible",
330 "sifive,fu540-c000-pdma");
331 g_free(nodename);
332
333 nodename = g_strdup_printf("/soc/cache-controller@%lx",
334 (long)memmap[SIFIVE_U_DEV_L2CC].base);
335 qemu_fdt_add_subnode(fdt, nodename);
336 qemu_fdt_setprop_cells(fdt, nodename, "reg",
337 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
338 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
339 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
340 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
341 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
342 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
343 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
344 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
345 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
346 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
347 qemu_fdt_setprop_string(fdt, nodename, "compatible",
348 "sifive,fu540-c000-ccache");
349 g_free(nodename);
350
351 phy_phandle = phandle++;
352 nodename = g_strdup_printf("/soc/ethernet@%lx",
353 (long)memmap[SIFIVE_U_DEV_GEM].base);
354 qemu_fdt_add_subnode(fdt, nodename);
355 qemu_fdt_setprop_string(fdt, nodename, "compatible",
356 "sifive,fu540-c000-gem");
357 qemu_fdt_setprop_cells(fdt, nodename, "reg",
358 0x0, memmap[SIFIVE_U_DEV_GEM].base,
359 0x0, memmap[SIFIVE_U_DEV_GEM].size,
360 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
361 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
362 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
363 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
364 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
365 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
366 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
367 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
368 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
369 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
370 sizeof(ethclk_names));
371 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
372 s->soc.gem.conf.macaddr.a, ETH_ALEN);
373 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
374 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
375
376 qemu_fdt_add_subnode(fdt, "/aliases");
377 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
378
379 g_free(nodename);
380
381 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
382 (long)memmap[SIFIVE_U_DEV_GEM].base);
383 qemu_fdt_add_subnode(fdt, nodename);
384 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
385 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
386 g_free(nodename);
387
388 nodename = g_strdup_printf("/soc/serial@%lx",
389 (long)memmap[SIFIVE_U_DEV_UART1].base);
390 qemu_fdt_add_subnode(fdt, nodename);
391 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
392 qemu_fdt_setprop_cells(fdt, nodename, "reg",
393 0x0, memmap[SIFIVE_U_DEV_UART1].base,
394 0x0, memmap[SIFIVE_U_DEV_UART1].size);
395 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
396 prci_phandle, PRCI_CLK_TLCLK);
397 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
398 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
399
400 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
401 g_free(nodename);
402
403 nodename = g_strdup_printf("/soc/serial@%lx",
404 (long)memmap[SIFIVE_U_DEV_UART0].base);
405 qemu_fdt_add_subnode(fdt, nodename);
406 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
407 qemu_fdt_setprop_cells(fdt, nodename, "reg",
408 0x0, memmap[SIFIVE_U_DEV_UART0].base,
409 0x0, memmap[SIFIVE_U_DEV_UART0].size);
410 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
411 prci_phandle, PRCI_CLK_TLCLK);
412 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
413 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
414
415 qemu_fdt_add_subnode(fdt, "/chosen");
416 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
417 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
418
419 g_free(nodename);
420
421 update_bootargs:
422 if (cmdline) {
423 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
424 }
425 }
426
427 static void sifive_u_machine_reset(void *opaque, int n, int level)
428 {
429 /* gpio pin active low triggers reset */
430 if (!level) {
431 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
432 }
433 }
434
435 static void sifive_u_machine_init(MachineState *machine)
436 {
437 const struct MemmapEntry *memmap = sifive_u_memmap;
438 SiFiveUState *s = RISCV_U_MACHINE(machine);
439 MemoryRegion *system_memory = get_system_memory();
440 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
441 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
442 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
443 target_ulong firmware_end_addr, kernel_start_addr;
444 uint32_t start_addr_hi32 = 0x00000000;
445 int i;
446 uint32_t fdt_load_addr;
447 uint64_t kernel_entry;
448
449 /* Initialize SoC */
450 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
451 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
452 &error_abort);
453 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
454 &error_abort);
455 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
456
457 /* register RAM */
458 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
459 machine->ram_size, &error_fatal);
460 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
461 main_mem);
462
463 /* register QSPI0 Flash */
464 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
465 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
466 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
467 flash0);
468
469 /* register gpio-restart */
470 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
471 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
472
473 /* create device tree */
474 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
475
476 if (s->start_in_flash) {
477 /*
478 * If start_in_flash property is given, assign s->msel to a value
479 * that representing booting from QSPI0 memory-mapped flash.
480 *
481 * This also means that when both start_in_flash and msel properties
482 * are given, start_in_flash takes the precedence over msel.
483 *
484 * Note this is to keep backward compatibility not to break existing
485 * users that use start_in_flash property.
486 */
487 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
488 }
489
490 switch (s->msel) {
491 case MSEL_MEMMAP_QSPI0_FLASH:
492 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
493 break;
494 case MSEL_L2LIM_QSPI0_FLASH:
495 case MSEL_L2LIM_QSPI2_SD:
496 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
497 break;
498 default:
499 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
500 break;
501 }
502
503 firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
504 start_addr, NULL);
505
506 if (machine->kernel_filename) {
507 kernel_start_addr = riscv_calc_kernel_start_addr(machine,
508 firmware_end_addr);
509
510 kernel_entry = riscv_load_kernel(machine->kernel_filename,
511 kernel_start_addr, NULL);
512
513 if (machine->initrd_filename) {
514 hwaddr start;
515 hwaddr end = riscv_load_initrd(machine->initrd_filename,
516 machine->ram_size, kernel_entry,
517 &start);
518 qemu_fdt_setprop_cell(s->fdt, "/chosen",
519 "linux,initrd-start", start);
520 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
521 end);
522 }
523 } else {
524 /*
525 * If dynamic firmware is used, it doesn't know where is the next mode
526 * if kernel argument is not set.
527 */
528 kernel_entry = 0;
529 }
530
531 /* Compute the fdt load address in dram */
532 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
533 machine->ram_size, s->fdt);
534 #if defined(TARGET_RISCV64)
535 start_addr_hi32 = start_addr >> 32;
536 #endif
537
538 /* reset vector */
539 uint32_t reset_vec[11] = {
540 s->msel, /* MSEL pin state */
541 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
542 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
543 0xf1402573, /* csrr a0, mhartid */
544 #if defined(TARGET_RISCV32)
545 0x0202a583, /* lw a1, 32(t0) */
546 0x0182a283, /* lw t0, 24(t0) */
547 #elif defined(TARGET_RISCV64)
548 0x0202b583, /* ld a1, 32(t0) */
549 0x0182b283, /* ld t0, 24(t0) */
550 #endif
551 0x00028067, /* jr t0 */
552 start_addr, /* start: .dword */
553 start_addr_hi32,
554 fdt_load_addr, /* fdt_laddr: .dword */
555 0x00000000,
556 /* fw_dyn: */
557 };
558
559 /* copy in the reset vector in little_endian byte order */
560 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
561 reset_vec[i] = cpu_to_le32(reset_vec[i]);
562 }
563 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
564 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
565
566 riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
567 memmap[SIFIVE_U_DEV_MROM].size,
568 sizeof(reset_vec), kernel_entry);
569 }
570
571 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
572 {
573 SiFiveUState *s = RISCV_U_MACHINE(obj);
574
575 return s->start_in_flash;
576 }
577
578 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
579 {
580 SiFiveUState *s = RISCV_U_MACHINE(obj);
581
582 s->start_in_flash = value;
583 }
584
585 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
586 const char *name, void *opaque,
587 Error **errp)
588 {
589 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
590 }
591
592 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
593 const char *name, void *opaque,
594 Error **errp)
595 {
596 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
597 }
598
599 static void sifive_u_machine_instance_init(Object *obj)
600 {
601 SiFiveUState *s = RISCV_U_MACHINE(obj);
602
603 s->start_in_flash = false;
604 s->msel = 0;
605 object_property_add(obj, "msel", "uint32",
606 sifive_u_machine_get_uint32_prop,
607 sifive_u_machine_set_uint32_prop, NULL, &s->msel);
608 object_property_set_description(obj, "msel",
609 "Mode Select (MSEL[3:0]) pin state");
610
611 s->serial = OTP_SERIAL;
612 object_property_add(obj, "serial", "uint32",
613 sifive_u_machine_get_uint32_prop,
614 sifive_u_machine_set_uint32_prop, NULL, &s->serial);
615 object_property_set_description(obj, "serial", "Board serial number");
616 }
617
618 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
619 {
620 MachineClass *mc = MACHINE_CLASS(oc);
621
622 mc->desc = "RISC-V Board compatible with SiFive U SDK";
623 mc->init = sifive_u_machine_init;
624 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
625 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
626 #if defined(TARGET_RISCV32)
627 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
628 #elif defined(TARGET_RISCV64)
629 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
630 #endif
631 mc->default_cpus = mc->min_cpus;
632
633 object_class_property_add_bool(oc, "start-in-flash",
634 sifive_u_machine_get_start_in_flash,
635 sifive_u_machine_set_start_in_flash);
636 object_class_property_set_description(oc, "start-in-flash",
637 "Set on to tell QEMU's ROM to jump to "
638 "flash. Otherwise QEMU will jump to DRAM "
639 "or L2LIM depending on the msel value");
640 }
641
642 static const TypeInfo sifive_u_machine_typeinfo = {
643 .name = MACHINE_TYPE_NAME("sifive_u"),
644 .parent = TYPE_MACHINE,
645 .class_init = sifive_u_machine_class_init,
646 .instance_init = sifive_u_machine_instance_init,
647 .instance_size = sizeof(SiFiveUState),
648 };
649
650 static void sifive_u_machine_init_register_types(void)
651 {
652 type_register_static(&sifive_u_machine_typeinfo);
653 }
654
655 type_init(sifive_u_machine_init_register_types)
656
657 static void sifive_u_soc_instance_init(Object *obj)
658 {
659 SiFiveUSoCState *s = RISCV_U_SOC(obj);
660
661 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
662 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
663
664 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
665 TYPE_RISCV_HART_ARRAY);
666 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
667 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
668 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
669 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
670
671 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
672 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
673
674 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
675 TYPE_RISCV_HART_ARRAY);
676
677 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
678 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
679 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
680 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
681 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
682 }
683
684 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
685 {
686 MachineState *ms = MACHINE(qdev_get_machine());
687 SiFiveUSoCState *s = RISCV_U_SOC(dev);
688 const struct MemmapEntry *memmap = sifive_u_memmap;
689 MemoryRegion *system_memory = get_system_memory();
690 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
691 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
692 char *plic_hart_config;
693 size_t plic_hart_config_len;
694 int i;
695 NICInfo *nd = &nd_table[0];
696
697 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
698 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
699 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
700 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
701
702 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
703 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
704 /*
705 * The cluster must be realized after the RISC-V hart array container,
706 * as the container's CPU object is only created on realize, and the
707 * CPU must exist and have been parented into the cluster before the
708 * cluster is realized.
709 */
710 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
711 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
712
713 /* boot rom */
714 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
715 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
716 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
717 mask_rom);
718
719 /*
720 * Add L2-LIM at reset size.
721 * This should be reduced in size as the L2 Cache Controller WayEnable
722 * register is incremented. Unfortunately I don't see a nice (or any) way
723 * to handle reducing or blocking out the L2 LIM while still allowing it
724 * be re returned to all enabled after a reset. For the time being, just
725 * leave it enabled all the time. This won't break anything, but will be
726 * too generous to misbehaving guests.
727 */
728 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
729 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
730 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
731 l2lim_mem);
732
733 /* create PLIC hart topology configuration string */
734 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
735 ms->smp.cpus;
736 plic_hart_config = g_malloc0(plic_hart_config_len);
737 for (i = 0; i < ms->smp.cpus; i++) {
738 if (i != 0) {
739 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
740 plic_hart_config_len);
741 } else {
742 strncat(plic_hart_config, "M", plic_hart_config_len);
743 }
744 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
745 }
746
747 /* MMIO */
748 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
749 plic_hart_config, 0,
750 SIFIVE_U_PLIC_NUM_SOURCES,
751 SIFIVE_U_PLIC_NUM_PRIORITIES,
752 SIFIVE_U_PLIC_PRIORITY_BASE,
753 SIFIVE_U_PLIC_PENDING_BASE,
754 SIFIVE_U_PLIC_ENABLE_BASE,
755 SIFIVE_U_PLIC_ENABLE_STRIDE,
756 SIFIVE_U_PLIC_CONTEXT_BASE,
757 SIFIVE_U_PLIC_CONTEXT_STRIDE,
758 memmap[SIFIVE_U_DEV_PLIC].size);
759 g_free(plic_hart_config);
760 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
761 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
762 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
763 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
764 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
765 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
766 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
767 SIFIVE_CLINT_TIMEBASE_FREQ, false);
768
769 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
770 return;
771 }
772 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
773
774 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
775 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
776 return;
777 }
778 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
779
780 /* Pass all GPIOs to the SOC layer so they are available to the board */
781 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
782
783 /* Connect GPIO interrupts to the PLIC */
784 for (i = 0; i < 16; i++) {
785 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
786 qdev_get_gpio_in(DEVICE(s->plic),
787 SIFIVE_U_GPIO_IRQ0 + i));
788 }
789
790 /* PDMA */
791 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
792 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
793
794 /* Connect PDMA interrupts to the PLIC */
795 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
796 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
797 qdev_get_gpio_in(DEVICE(s->plic),
798 SIFIVE_U_PDMA_IRQ0 + i));
799 }
800
801 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
802 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
803 return;
804 }
805 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
806
807 /* FIXME use qdev NIC properties instead of nd_table[] */
808 if (nd->used) {
809 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
810 qdev_set_nic_properties(DEVICE(&s->gem), nd);
811 }
812 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
813 &error_abort);
814 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
815 return;
816 }
817 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
818 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
819 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
820
821 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
822 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
823
824 create_unimplemented_device("riscv.sifive.u.dmc",
825 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
826
827 create_unimplemented_device("riscv.sifive.u.l2cc",
828 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
829 }
830
831 static Property sifive_u_soc_props[] = {
832 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
833 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
834 DEFINE_PROP_END_OF_LIST()
835 };
836
837 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
838 {
839 DeviceClass *dc = DEVICE_CLASS(oc);
840
841 device_class_set_props(dc, sifive_u_soc_props);
842 dc->realize = sifive_u_soc_realize;
843 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
844 dc->user_creatable = false;
845 }
846
847 static const TypeInfo sifive_u_soc_type_info = {
848 .name = TYPE_RISCV_U_SOC,
849 .parent = TYPE_DEVICE,
850 .instance_size = sizeof(SiFiveUSoCState),
851 .instance_init = sifive_u_soc_instance_init,
852 .class_init = sifive_u_soc_class_init,
853 };
854
855 static void sifive_u_soc_register_types(void)
856 {
857 type_register_static(&sifive_u_soc_type_info);
858 }
859
860 type_init(sifive_u_soc_register_types)
AR7 emulation for QEMU