| commit | d31e970a01e7399b9cd43ec0dc00c857d968987e | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 15 Dec 2020 01:56:54 +0000 (14 17:56 -0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 18 Dec 2020 05:56:44 +0000 (17 21:56 -0800) | ||
| tree | f7e62273c6e9697bd2cc28a88e4aad8ef21adc69 | treesnapshot (tar.gz zip) |
| parent | 3ed2b8ac2dacc22c088ec5793ecde31db2fa0414 | commitdiff |
riscv/opentitan: Update the OpenTitan memory layout
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
| hw/riscv/opentitan.c | diffblobblamehistory | |
| include/hw/riscv/opentitan.h | diffblobblamehistory |