2020-09-09 | Bin Meng | hw/riscv: Move sifive_clint model to hw/intc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_gpio model to hw/gpio Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_otp model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_e_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: sifive_u: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: clint: Avoid using hard-coded timebase frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Hook GPIO controllers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/arm: xlnx: Set all boards' GEM 'phy-addr' property... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/net: cadence_gem: Add a new 'phy-addr' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/dma: Add SiFive platform DMA controller emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/sd: Add Cadence SDHCI emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/char: Add Microchip PolarFire SoC MMUART emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Initial support for Microchip PolarFire SoC... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | target/riscv: cpu: Set reset vector based on the configured... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: hart: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | target/riscv: cpu: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Nathan Chancellor | riscv: sifive_test: Allow 16-bit writes to memory region Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Yifei Jiang | target/riscv: Fix bug in getting trap cause name for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Support the Virtual Instruction fault Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Return the exception from invalid CSR... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Support the v0.6 Hypervisor extension... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Only support little endian guests Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Only support a single VSXL length Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Update the CSRs to the v0.6 Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Update the Hypervisor trap return/entry Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Fix the interrupt cause code Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Convert MSTATUS MTL to GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Don't allow guest to write to htinst Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Do two-stage lookups on hlv/hlvx/hsv... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Allow generating hlv/hlvx/hsv instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Allow setting a two-stage lookup in the... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: virt: Allow creating multiple NUMA sockets Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: spike: Allow creating multiple NUMA sockets Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Add helpers for RISC-V multi-socket NUMA... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of PLIC Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of CLINT Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Honour source priorities Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Don't allow repeat interrupts on... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Update the pending irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Zong Li | target/riscv: Change the TLB page size depends on PMP... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Zong Li | target/riscv: Fix the translation of physical address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | gitlab-ci/opensbi: Update GitLab CI to build generic... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | hw/riscv: spike: Change the default bios to use generic... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | hw/riscv: Use pre-built bios image of generic platform... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | roms/Makefile: Build the generic platform for RISC... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | roms/opensbi: Upgrade from v0.7 to v0.8 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | configure: Create symbolic links for pc-bios/*.elf... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Hou Weiying | riscv: Fix bug in setting pmpcfg CSR for RISCV64 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | hw/riscv: sifive_u: Add a dummy L2 cache controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | LIU Zhiwei | target/riscv: check before allocating TCG temps Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | LIU Zhiwei | target/riscv: Clean up fmv.w.x Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Richard Henderson | target/riscv: Check nanboxed inputs in trans_rvf.inc.c Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Richard Henderson | target/riscv: Check nanboxed inputs to fp helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Richard Henderson | target/riscv: Generate nanboxed results from trans_rvf... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Richard Henderson | target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Richard Henderson | target/riscv: Generate nanboxed results from fp helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-22 | Zong Li | target/riscv: Fix the range of pmpcfg of CSR funcion... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-22 | Bin Meng | hw/riscv: sifive_e: Correct debug block size Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-22 | LIU Zhiwei | target/riscv: fix vector index load/store constraints Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-22 | LIU Zhiwei | target/riscv: Quiet Coverity complains about vamo* Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-22 | Jessica Clarke | goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Alexandre Mergnat | target/riscv: Fix pmp NA4 implementation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Liao Pingfang | tcg/riscv: Remove superfluous breaks Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Alistair Francis | hw/char: Convert the Ibex UART to use the registerfields API Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Alistair Francis | hw/char: Convert the Ibex UART to use the qdev Clock... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Frank Chang | target/riscv: fix vill bit index in vtype register Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Frank Chang | target/riscv: fix return value of do_opivx_widen() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Frank Chang | target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Frank Chang | target/riscv: fix rsub gvec tcg_assert_listed_vecop... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Bin Meng | hw/riscv: Modify MROM size to end at 0x10000 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Atish Patra | RISC-V: Support 64 bit start address Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Atish Patra | riscv: Add opensbi firmware dynamic support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Atish Patra | RISC-V: Copy the fdt in dram instead of ROM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Atish Patra | riscv: Unify Qemu's reset vector code path Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Bin Meng | hw/riscv: virt: Sort the SoC memmap table entries Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-14 | Bin Meng | MAINTAINERS: Add an entry for OpenSBI firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: configure and turn on vector extension... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector compress instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector register gather instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector slide instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: floating-point scalar move instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: integer scalar move instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: integer extract instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector element index instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector iota instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: set-X-first mask bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vmfirst find-first-set mask bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector mask population count vmpopc Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector mask-register logical instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector widening floating-point reduction... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector single-width floating-point reduction... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector wideing integer reduction instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: vector single-width integer reduction... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: narrowing floating-point/integer type... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-07-02 | LIU Zhiwei | target/riscv: widening floating-point/integer type... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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