target/riscv: Fix the interrupt cause code
commit84b1c04bbaf48798a535b38410a0bf839f4a1943
authorAlistair Francis <alistair.francis@wdc.com>
Wed, 12 Aug 2020 19:13:30 +0000 (12 12:13 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 25 Aug 2020 16:11:36 +0000 (25 09:11 -0700)
tree6b2d2c7f29bc834e39c8b60fc36158bd53adec63
parent9034e90ad9959b89da32978e3b6d71b7069050a5
target/riscv: Fix the interrupt cause code

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
target/riscv/cpu_helper.c