| commit | fbcbafa2c1c33ae6630e7717f7f4141befb5b31a | |
| author | Frank Chang <frank.chang@sifive.com> | |
| Fri, 10 Jul 2020 10:48:18 +0000 (10 18:48 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 14 Jul 2020 00:25:37 +0000 (13 17:25 -0700) | ||
| tree | a91a4fa832380d21ccfae7bae7760e2769e32e94 | treesnapshot (tar.gz zip) |
| parent | a69f97c1110205bc173657c77ce2d16877cad683 | commitdiff |
target/riscv: fix vill bit index in vtype register
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.h | diffblobblamehistory |