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2020-09-09	Bin Meng	hw/riscv: Move sifive_u_otp model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_u_prci model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_e_prci model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: sifive_u: Connect a DMA controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: clint: Avoid using hard-coded timebase frequency Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Hook GPIO controllers Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/arm: xlnx: Set all boards' GEM 'phy-addr' property... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/net: cadence_gem: Add a new 'phy-addr' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect a DMA controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/dma: Add SiFive platform DMA controller emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/sd: Add Cadence SDHCI emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/char: Add Microchip PolarFire SoC MMUART emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Initial support for Microchip PolarFire SoC... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	target/riscv: cpu: Set reset vector based on the configured... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: hart: Add a new 'resetvec' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	target/riscv: cpu: Add a new 'resetvec' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	gitlab-ci/opensbi: Update GitLab CI to build generic... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: spike: Change the default bios to use generic... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: Use pre-built bios image of generic platform... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	roms/Makefile: Build the generic platform for RISC... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	roms/opensbi: Upgrade from v0.7 to v0.8 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	configure: Create symbolic links for pc-bios/*.elf... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: sifive_u: Add a dummy L2 cache controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-21	Bin Meng	hw/sd: Correct the maximum size of a Standard Capacity... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-21	Bin Meng	hw/sd: Fix incorrect populated function switch status... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-07-14	Bin Meng	hw/riscv: Modify MROM size to end at 0x10000 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-07-14	Bin Meng	hw/riscv: virt: Sort the SoC memmap table entries Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add a dummy DDR memory controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Sort the SoC memmap table entries Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Support different boot source per... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive: Change SiFive E/U CPU reset vector... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	target/riscv: Rename IBEX CPU init routine Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add a new property msel for MSEL... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Rename serial property get/set... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add reset functionality Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Do not blindly trigger output... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Hook a GPIO controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Add a new 'ngpio' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Clean up the codes Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Generate device tree node for OTP Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Simplify the GEM IRQ connect code... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: opentitan: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_e: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Keep the CPU init routine names consistent Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the imacu CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the gcsu CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the base CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	hw/riscv: virt: Remove the riscv_ prefix of the machine... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	hw/riscv: sifive_u: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	riscv: Change the default behavior if no -bios option... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	riscv: Suppress the error report for QEMU testing with... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree

AR7 emulation for QEMU

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