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target/riscv: Rename IBEX CPU init routine
2020-06-19
Bin Meng
ta
r
get/ris
c
v: R
e
name IBEX CPU init
r
outine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
h
w
/
riscv:
s
i
five_u
:
A
d
d a new property
msel for MSE
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Rename
serial property get/se
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_
u
: Add rese
t
functi
o
nality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw/riscv: si
f
ive_gpio: Do not
b
lindly t
r
igger o
u
tp
u
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_u: Hook a G
P
IO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
isc
v
: sifive_gpio: Ad
d
a
n
e
w 'ngpio' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sif
i
ve_gpio: Cl
e
an up the cod
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Generate d
e
vice tree node for OT
P
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Me
n
g
hw/ri
s
cv: s
i
five_u: Simpli
f
y the GEM
IR
Q
connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
hw/riscv: op
e
ntitan: Remove
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Men
g
hw/riscv: sif
i
v
e_e
:
R
emove the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv:
Keep the CPU init routine names cons
i
s
tent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gene
r
alize C
P
U
i
n
it r
o
utine for
t
he
ima
c
u CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
s
cv: Generalize CPU init ro
u
t
i
ne for th
e
gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: General
i
ze CPU init ro
u
tin
e
f
or the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w
/ris
c
v: v
i
r
t: R
e
move the riscv_ pref
i
x
of the
machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Me
n
g
hw/riscv: sifive_u: Remove
the
r
i
s
cv_ p
r
efix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n
Meng
riscv: Change the default beha
v
i
o
r
if no -bios
option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv: Suppress the
error r
e
port for
Q
EMU testi
n
g with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
roms
:
opensbi: Upgrade from v
0
.
6 to
v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/risc
v
: Genera
t
e correc
t
"
mmu-type" for 32-bit
mach
i
n
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
riscv/sifive_u: Add a serial property
t
o
the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin M
e
ng
gitlab-ci
.
y
m
l:
A
d
d jobs to build O
p
enS
B
I
f
i
rmware binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Men
g
riscv: sifive_u: Update
B
IOS_FILENA
M
E for
3
2-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
M
eng
roms
:
opensbi: Add 32-bit firmware i
m
age for sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bi
n
Men
g
roms: opensbi: Upg
r
ade from v0
.
5
t
o
v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bi
n
Meng
h
w: net
:
cadence_gem: Fix build errors i
n
DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin M
e
ng
riscv: vir
t
: Allow PCI
a
d
dres
s
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
B
i
n Meng
riscv: sifive
_
u: Add ethernet0 to
t
he
a
l
iases nod
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Men
g
r
i
scv
:
hw: Drop "clock-frequency" property of cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
ri
s
cv: Skip checkin
g
CSR privileg
e
le
v
el in debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
i
f
ive_
u
:
U
pdate model
a
nd
c
o
m
patible st
r
ings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
riscv
:
s
i
five_
u
:
Remove handcra
f
ted clock nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
sifive_u: Fix bro
k
en GEM suppo
r
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: sifive_u: I
n
s
tantiate OTP memory with
a
ser
i
al
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive:
Implement a model for SiFive FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
ris
c
v: r
o
ms:
Update
d
e
fault bios for sifive_u m
a
chine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv:
s
ifive_
u
: Change UA
R
T node
n
a
me in device tr
e
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: sifive_u: Update
U
ART base addresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: sifive_
u
: Referen
c
e PRCI clocks in UART a
n
d
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
ri
s
cv: sifive_u:
A
dd PRCI b
l
ock to t
h
e SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive_
u
: Gene
r
ate
hfcl
k
and rtcclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: si
f
ive: Implement PRCI
m
ode
l
for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: sifive_u:
U
pda
t
e PL
I
C h
a
rt topol
o
gy configuration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sifive_u: Update hart configura
t
ion to
r
eflec
t
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: sifive_u: Set the mini
m
um number
o
f
cpus to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv: hart:
A
d
d a
"
hart
i
d
-
base"
p
roperty to RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: hart: Extract ha
r
t realize to a separate rout
i
ne
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: Ad
d
a
sifive_cpu
.
h
to inc
l
u
d
e
b
ot
h
E
a
n
d
U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
n
g
riscv:
s
i
f
ive_e:
D
r
o
p sifive_mmi
o
_
e
mu
l
ate()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive
_
e
:
prci:
Update the
PRCI register block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifive_
e
: prci: Fix a typo of h
f
xos
c
cfg register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Rename
s
ifive_prc
i
.
{c
,
h} to si
f
ive
_
e_p
r
ci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Remove the unnecessary include of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
r
i
scv: roms:
R
e
m
ov
e
e
x
ecuta
b
l
e
a
t
tribute of o
p
ensbi
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: h
w
: Remove the
u
nnecessary
i
n
c
l
ude
of target
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: hw:
Change to us
e
qemu
_
log_mas
k
(LOG_GUEST_
E
RROR
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
eng
ris
c
v: hw: C
h
ange c
r
eate_fdt() to return voi
d
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
ri
s
cv
:
hw
:
R
e
m
ove no
t
n
eed
e
d P
L
IC properties in de
v
ic
e
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv: hw: Use qemu_fdt_set
p
r
op_cel
l
(
) fo
r
pro
p
e
rty
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: hw:
R
emove superfluous "li
n
ux, phandle" property
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Men
g
r
iscv: hw: Re
m
ove
d
uplicated
"
hw
/
hw
.
h"
i
nclusion
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
eng
risc
v
: sifi
v
e_tes
t
: Add re
s
et functionality
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
n
g
riscv: hmp: Add a co
m
mand to sho
w
virt
u
al memory mapp
i
ngs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: R
e
so
l
ve full
path of
th
e
given bios
i
mage
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: Add a
helper routi
n
e for
fin
d
ing f
i
r
mwa
r
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
M
e
ng
r
iscv: rv32
:
Root page table
address can be larger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-08-13
Bin Meng
ris
c
v:
r
oms: Fix m
a
ke rules for b
u
ilding si
f
ive_u bios
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-27
Bin
M
eng
ris
c
v:
si
f
ive_
u
: Upd
a
te th
e
p
l
ic h
a
rt co
n
f
i
g
t
o
support
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-27
Bin Meng
riscv: sifi
v
e_u: Do not create hard-
c
oded
p
handles
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-06-24
Bin Meng
riscv
:
v
irt:
C
orrect pci "
b
us
-
rang
e
"
encod
i
ng
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-03-19
Bin Meng
riscv: sifive_u: C
o
rrect
UA
R
T0's IRQ in the dev
i
c
e
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-03-19
B
in Meng
riscv: sifiv
e
_uart:
G
enerate TX int
e
rrup
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree