2020-12-18 | Vitaly Wool | hw/riscv: microchip_pfsoc: add QSPI NOR flash Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Anup Patel | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-14 | Alistair Francis | intc/ibex_plic: Ensure we don't loose interrupts Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...828e7c3f85293a09a65b12.1605136387.git.alistair.francis@wdc.com |
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2020-11-14 | Alistair Francis | intc/ibex_plic: Fix some typos in the comments Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...67ac909926368d1bcb7cf5.1605136387.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | hw/intc/ibex_plic: Clear the claim register when read Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | target/riscv: Split the Hypervisor execute load helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | target/riscv: Remove the hyp load and store functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | target/riscv: Remove the HS_TWO_STAGE flag Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | target/riscv: Set the virtualised MMU mode when doing... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...53f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com |
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2020-11-09 | Alistair Francis | target/riscv: Add a virtualised MMU Mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com |
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2020-11-03 | Xinhao Zhang | target/riscv/csr.c : add space before the open parenthesis '(' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Hook the I2C1 controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Correct DDR memory map Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Map the reserved memory... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the SYSREG module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC SYSREG module... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the IOSCB module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC IOSCB module support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect DDR memory controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC DDR Memory Controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Document where to look at... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add sifive_plic vmstate Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add V extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add H extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add PMP state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add basic vmstate description of CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Merge m/vsstatus and m/vsstatush into... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Anup Patel | hw/riscv: virt: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Anup Patel | hw/riscv: sifive_u: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add backend drive support Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add write function and write... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Yifei Jiang | target/riscv: raise exception to HS-mode at get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Alistair Francis | hw/riscv: Load the kernel after the firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...2090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com |
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2020-10-22 | Alistair Francis | hw/riscv: Add a riscv_is_32_bit() function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...9356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com |
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2020-10-22 | Alistair Francis | hw/riscv: Return the end address of the loaded firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...3262248b040563716628b2.1602634524.git.alistair.francis@wdc.com |
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2020-10-22 | Alistair Francis | hw/riscv: sifive_u: Allow specifying the CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com |
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2020-10-22 | Georg Kotheimer | target/riscv: Fix implementation of HLVX.WU instruction Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Georg Kotheimer | target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_inte... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Georg Kotheimer | target/riscv: Fix update of hstatus.SPVP Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Bin Meng | hw/intc: Move sifive_plic.h to the include directory Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Alistair Francis | riscv: Convert interrupt logs to use qemu_log_mask() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com |
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2020-09-25 | Alistair Francis | core/register: Specify instance_size in the TypeInfo Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...61d266557d3173bf160524.1598376594.git.alistair.francis@wdc.com> |
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2020-09-25 | BALATON Zoltan | load_elf: Remove unused address variables from callers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Sort the Kconfig options in alphabetical... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Drop CONFIG_SIFIVE Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Always build riscv_hart.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_test model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_uart model to hw/char Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move riscv_htif model to hw/char Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_plic model to hw/intc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_clint model to hw/intc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_gpio model to hw/gpio Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_otp model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Move sifive_e_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: sifive_u: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: clint: Avoid using hard-coded timebase frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Hook GPIO controllers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/arm: xlnx: Set all boards' GEM 'phy-addr' property... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/net: cadence_gem: Add a new 'phy-addr' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/dma: Add SiFive platform DMA controller emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/sd: Add Cadence SDHCI emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/char: Add Microchip PolarFire SoC MMUART emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: Initial support for Microchip PolarFire SoC... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | target/riscv: cpu: Set reset vector based on the configured... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | hw/riscv: hart: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Bin Meng | target/riscv: cpu: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Nathan Chancellor | riscv: sifive_test: Allow 16-bit writes to memory region Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-09-09 | Yifei Jiang | target/riscv: Fix bug in getting trap cause name for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Support the Virtual Instruction fault Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com ...5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Return the exception from invalid CSR... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com ...b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Support the v0.6 Hypervisor extension... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...e0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com ...e0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Only support little endian guests Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...8e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com ...8e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Only support a single VSXL length Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com ...750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Update the CSRs to the v0.6 Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...96c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com ...96c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Update the Hypervisor trap return/entry Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...6e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com ...6e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Fix the interrupt cause code Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...3275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com ...3275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Convert MSTATUS MTL to GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com ...a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Don't allow guest to write to htinst Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com ...eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Do two-stage lookups on hlv/hlvx/hsv... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com ...950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Allow generating hlv/hlvx/hsv instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com ...98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Alistair Francis | target/riscv: Allow setting a two-stage lookup in the... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com ...e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: virt: Allow creating multiple NUMA sockets Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: spike: Allow creating multiple NUMA sockets Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Add helpers for RISC-V multi-socket NUMA... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of PLIC Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of CLINT Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Honour source priorities Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...a88e09a28206063cf85d48.1595655188.git.alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Don't allow repeat interrupts on... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com> |
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2020-08-22 | Alistair Francis | hw/intc: ibex_plic: Update the pending irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com> |
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2020-08-22 | Zong Li | target/riscv: Change the TLB page size depends on PMP... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Zong Li | target/riscv: Fix the translation of physical address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | gitlab-ci/opensbi: Update GitLab CI to build generic... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | hw/riscv: spike: Change the default bios to use generic... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | hw/riscv: Use pre-built bios image of generic platform... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-08-22 | Bin Meng | roms/Makefile: Build the generic platform for RISC... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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