2020-12-18 | Alistair Francis | riscv/opentitan: Update the OpenTitan memory layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: Use the CPU to determine if 32-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: cpu: Set XLEN independently from target Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: csr: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: cpu_helper: Remove compile time XLEN... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: cpu: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: Specify the XLEN for CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: Add a riscv_cpu_is_32bit() helper function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: fpu_helper: Match function defs in HELPER... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: sifive_u: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: spike: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: virt: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: boot: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | riscv: virt: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | riscv: spike: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | hw/riscv: Expand the is 32-bit check to support more... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alistair Francis | intc/ibex_plic: Clear interrupts that occur during... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Alex Richardson | target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Yifei Jiang | target/riscv: Fix the bug of HLVX/HLV/HSV Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Xinhao Zhang | hw/core/register.c: Don't use '#' flag of printf format Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Vitaly Wool | hw/riscv: microchip_pfsoc: add QSPI NOR flash Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-12-18 | Anup Patel | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-14 | Alistair Francis | intc/ibex_plic: Ensure we don't loose interrupts Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-14 | Alistair Francis | intc/ibex_plic: Fix some typos in the comments Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | hw/intc/ibex_plic: Clear the claim register when read Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | target/riscv: Split the Hypervisor execute load helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | target/riscv: Remove the hyp load and store functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | target/riscv: Remove the HS_TWO_STAGE flag Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | target/riscv: Set the virtualised MMU mode when doing... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-09 | Alistair Francis | target/riscv: Add a virtualised MMU Mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Xinhao Zhang | target/riscv/csr.c : add space before the open parenthesis '(' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Hook the I2C1 controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Correct DDR memory map Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Map the reserved memory... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the SYSREG module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC SYSREG module... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the IOSCB module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC IOSCB module support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect DDR memory controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC DDR Memory Controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Document where to look at... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Add sifive_plic vmstate Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Add V extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Add H extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Add PMP state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Add basic vmstate description of CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Yifei Jiang | target/riscv: Merge m/vsstatus and m/vsstatush into... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Anup Patel | hw/riscv: virt: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-11-03 | Anup Patel | hw/riscv: sifive_u: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add backend drive support Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add write function and write... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Yifei Jiang | target/riscv: raise exception to HS-mode at get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Alistair Francis | hw/riscv: Load the kernel after the firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Alistair Francis | hw/riscv: Add a riscv_is_32_bit() function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Alistair Francis | hw/riscv: Return the end address of the loaded firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Alistair Francis | hw/riscv: sifive_u: Allow specifying the CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Georg Kotheimer | target/riscv: Fix implementation of HLVX.WU instruction Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Georg Kotheimer | target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_inte... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Georg Kotheimer | target/riscv: Fix update of hstatus.SPVP Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Bin Meng | hw/intc: Move sifive_plic.h to the include directory Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-10-22 | Alistair Francis | riscv: Convert interrupt logs to use qemu_log_mask() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-25 | Alistair Francis | core/register: Specify instance_size in the TypeInfo Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-25 | BALATON Zoltan | load_elf: Remove unused address variables from callers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Sort the Kconfig options in alphabetical... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Drop CONFIG_SIFIVE Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Always build riscv_hart.c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_test model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_uart model to hw/char Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move riscv_htif model to hw/char Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_plic model to hw/intc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_clint model to hw/intc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_gpio model to hw/gpio Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_otp model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_u_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Move sifive_e_prci model to hw/misc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: sifive_u: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: clint: Avoid using hard-coded timebase frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Hook GPIO controllers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/arm: xlnx: Set all boards' GEM 'phy-addr' property... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/net: cadence_gem: Add a new 'phy-addr' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a DMA controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/dma: Add SiFive platform DMA controller emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/sd: Add Cadence SDHCI emulation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/char: Add Microchip PolarFire SoC MMUART emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: Initial support for Microchip PolarFire SoC... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | target/riscv: cpu: Set reset vector based on the configured... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | hw/riscv: hart: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Bin Meng | target/riscv: cpu: Add a new 'resetvec' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Nathan Chancellor | riscv: sifive_test: Allow 16-bit writes to memory region Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-09-09 | Yifei Jiang | target/riscv: Fix bug in getting trap cause name for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Support the Virtual Instruction fault Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Return the exception from invalid CSR... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Support the v0.6 Hypervisor extension... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Only support little endian guests Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Only support a single VSXL length Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
2020-08-25 | Alistair Francis | target/riscv: Update the CSRs to the v0.6 Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
commitcommitdifftree |
next |