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target/riscv/csr.c : add space before the open parenthesis '('
2020-11-03 Xinhao Zhangtarget/riscv/csr.c : add space before the open parenthesis '('
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Hook the I2C1 controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Correct DDR memory map
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Map the reserved memory...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect the SYSREG module
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC SYSREG module...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect the IOSCB module
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC IOSCB module support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect DDR memory controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC DDR Memory Controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Document where to look at...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add sifive_plic vmstate
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add V extension state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add H extension state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add PMP state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add basic vmstate description of CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Merge m/vsstatus and m/vsstatush into...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Anup Patelhw/riscv: virt: Allow passing custom DTB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Anup Patelhw/riscv: sifive_u: Allow passing custom DTB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Green Wanhw/misc/sifive_u_otp: Add backend drive support
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Green Wanhw/misc/sifive_u_otp: Add write function and write...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Yifei Jiangtarget/riscv: raise exception to HS-mode at get_physical_address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Load the kernel after the firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Add a riscv_is_32_bit() function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Return the end address of the loaded firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: sifive_u: Allow specifying the CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Georg Kotheimertarget/riscv: Fix implementation of HLVX.WU instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Georg Kotheimertarget/riscv: Fix update of hstatus.GVA in riscv_cpu_do_inte...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Georg Kotheimertarget/riscv: Fix update of hstatus.SPVP
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Bin Menghw/intc: Move sifive_plic.h to the include directory
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francisriscv: Convert interrupt logs to use qemu_log_mask()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-25 Alistair Franciscore/register: Specify instance_size in the TypeInfo
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-25 BALATON Zoltanload_elf: Remove unused address variables from callers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Sort the Kconfig options in alphabetical...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Drop CONFIG_SIFIVE
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Always build riscv_hart.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_test model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_uart model to hw/char
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move riscv_htif model to hw/char
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_plic model to hw/intc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_clint model to hw/intc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_gpio model to hw/gpio
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_u_otp model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_u_prci model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_e_prci model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: sifive_u: Connect a DMA controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: clint: Avoid using hard-coded timebase frequency
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Hook GPIO controllers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/arm: xlnx: Set all boards' GEM 'phy-addr' property...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/net: cadence_gem: Add a new 'phy-addr' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect a DMA controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/dma: Add SiFive platform DMA controller emulation
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect a Cadence SDHCI...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/sd: Add Cadence SDHCI emulation
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/char: Add Microchip PolarFire SoC MMUART emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Initial support for Microchip PolarFire SoC...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Mengtarget/riscv: cpu: Set reset vector based on the configured...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: hart: Add a new 'resetvec' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Mengtarget/riscv: cpu: Add a new 'resetvec' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Nathan Chancellorriscv: sifive_test: Allow 16-bit writes to memory region
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Yifei Jiangtarget/riscv: Fix bug in getting trap cause name for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Support the Virtual Instruction fault
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Return the exception from invalid CSR...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Support the v0.6 Hypervisor extension...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Only support little endian guests
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Only support a single VSXL length
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Update the CSRs to the v0.6 Hyp extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Update the Hypervisor trap return/entry
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Fix the interrupt cause code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Convert MSTATUS MTL to GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Don't allow guest to write to htinst
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Do two-stage lookups on hlv/hlvx/hsv...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Allow generating hlv/hlvx/hsv instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Allow setting a two-stage lookup in the...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Anup Patelhw/riscv: virt: Allow creating multiple NUMA sockets
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Anup Patelhw/riscv: spike: Allow creating multiple NUMA sockets
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Anup Patelhw/riscv: Add helpers for RISC-V multi-socket NUMA...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Anup Patelhw/riscv: Allow creating multiple instances of PLIC
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-25 Anup Patelhw/riscv: Allow creating multiple instances of CLINT
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Honour source priorities
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Don't allow repeat interrupts on...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Update the pending irqs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Zong Litarget/riscv: Change the TLB page size depends on PMP...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Zong Litarget/riscv: Fix the translation of physical address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menggitlab-ci/opensbi: Update GitLab CI to build generic...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menghw/riscv: spike: Change the default bios to use generic...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menghw/riscv: Use pre-built bios image of generic platform...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengroms/Makefile: Build the generic platform for RISC...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengroms/opensbi: Upgrade from v0.7 to v0.8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengconfigure: Create symbolic links for pc-bios/*.elf...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Hou Weiyingriscv: Fix bug in setting pmpcfg CSR for RISCV64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menghw/riscv: sifive_u: Add a dummy L2 cache controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 LIU Zhiweitarget/riscv: check before allocating TCG temps
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 LIU Zhiweitarget/riscv: Clean up fmv.w.x
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Check nanboxed inputs in trans_rvf.inc.c
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Check nanboxed inputs to fp helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Generate nanboxed results from trans_rvf...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU