| 2020-03-17 | Bin Meng | roms: opensbi: Add 32-bit firmware image for sifive_u... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Bin Meng | roms: opensbi: Upgrade from v0.5 to v0.6 Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Alistair Francis | target/riscv: Correctly implement TSR trap Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Palmer Dabbelt | RISC-V: Add a missing "," in riscv_excp_names Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Anup Patel | hw/riscv: Provide rdtime callback for TCG in CLINT... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Anup Patel | target/riscv: Emulate TIME CSRs for privileged mode Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Bin Meng | riscv: virt: Allow PCI address 0 Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow enabling the Hypervisor extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the MSTATUS_MPV_ISSET helper macro Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the 32-bit MSTATUSH CSR Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set htval and mtval2 on execptions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Raise the new execptions when 2nd stage... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Implement second stage MMU Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow specifying MMU stage Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Respect MPRV and SPRV for floating point ops Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Mark both sstatus and msstatus_hs as... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Disable guest FP support based on virtual... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Only set TB flags with FP status if enabled Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Remove the hret instruction Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hfence instructions Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor trap return support Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hypvervisor trap support Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Generate illegal instruction on WFI when V=1 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/ricsv: Flush the TLB on virtulisation mode changes Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for virtual interrupt setting Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the SIP CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the MIE CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set VS bits in mideleg for Hyp extension Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add virtual register swapping function Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor machine CSRs accesses Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor virtual CSRs accesses Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor CSR access functions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Dump Hypervisor registers if enabled Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Print priv and virt in disas log Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Fix CSR perm checking for HS mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the force HS exception mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the virtulisation mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Rename the H irqs to VS irqs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the new execption numbers Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor CSRs to CPUState Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Convert MIP CSR to target_ulong Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | MAINTAINERS: Add maintainer entry for Goldfish RTC Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv: virt: Use Goldfish RTC device Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Acked-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | hw: rtc: Add Goldfish RTC device Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Keith Packard | riscv: Separate FPU register size from core register... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv/virt: Add syscon reboot and poweroff DT nodes Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: update mstatus.SD when FS is set dirty Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: fsd/fsw doesn't dirty FP state Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: Fix tb->flags FS status Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Yiting Wang | riscv: Set xPIE to 1 after xRET Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Pan Nengyuan | riscv/sifive_u: fix a memory leak in soc_realize() Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Zhuang, Siwei (Data6... | hw/riscv: Add optional symbol callback ptr to riscv_load_ker... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Palmer Dabbelt | RISC-V: virt: This is a "sifive,test1" test finisher Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-14 | Alistair Francis | riscv/virt: Increase flash size Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-11-14 | Alistair Francis | opensbi: Upgrade from v0.4 to v0.5 Palmer Dabbelt (1): Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> |
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| 2019-11-14 | Alistair Francis | target/riscv: Remove atomic accesses to MIP CSR Reviewed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> |
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| 2019-11-14 | hiroyuki.obinata | remove unnecessary ifdef TARGET_RISCV64 Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-11-01 | Palmer Dabbelt | MAINTAINERS: Change to my personal email address Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> |
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| 2019-10-28 | Dayeol Lee | target/riscv: PMP violation due to wrong size parameter Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/boot: Fix possible memory leak Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Jonathan Behrens | target/riscv: Make the priv register writable by GDB Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Jonathan Behrens | target/riscv: Expose "priv" register for GDB for reads Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Jonathan Behrens | target/riscv: Tell gdbstub the correct number of CSRs Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Jump to pflash if specified Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Add the PFlash CFI01 device Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Manually define the machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add the start-in-flash property Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Manually define the machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add QSPI memory region Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add L2-LIM cache memory Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Giuseppe Musacchio | linux-user/riscv: Propagate fault address Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Bin Meng | riscv: sifive_u: Add ethernet0 to the aliases node Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Bin Meng | riscv: hw: Drop "clock-frequency" property of cpu nodes Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Palmer Dabbelt | RISC-V: Implement cpu_do_transaction_failed Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Palmer Dabbelt | RISC-V: Handle bus errors in the page table walker Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-10-28 | Bin Meng | riscv: Skip checking CSR privilege level in debugger... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | KONRAD Frederic | gdbstub: riscv: fix the fflags registers Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Use TB_FLAGS_MSTATUS_FS for floating... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Fix mstatus dirty mask Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Atish Patra | target/riscv: Use both register name and ABI name Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Update model and compatible strings... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Remove handcrafted clock nodes for... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Fix broken GEM support Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Instantiate OTP memory with a serial... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive: Implement a model for SiFive FU540 OTP Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: roms: Update default bios for sifive_u machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Change UART node name in device tree Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Update UART base addresses and IRQs Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Reference PRCI clocks in UART and... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Add PRCI block to the SoC Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Generate hfclk and rtcclk nodes Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive: Implement PRCI model for FU540 Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Update PLIC hart topology configuration... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Update hart configuration to reflect... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Set the minimum number of cpus to 2 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hart: Add a "hartid-base" property to RISC-V... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hart: Extract hart realize to a separate routine Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: Add a sifive_cpu.h to include both E and U cpu... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_e: Drop sifive_mmio_emulate() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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