| commit | ab67a1d07a4f6f1b4d577c5c47013273b9804551 | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Sat, 1 Feb 2020 01:01:46 +0000 (31 17:01 -0800) | ||
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | |
| Thu, 27 Feb 2020 21:45:26 +0000 (27 13:45 -0800) | ||
| tree | 307397af927be61674a0ed9e47fb7542683cf2d2 | treesnapshot (tar.gz zip) |
| parent | bd023ce33b85d73791b7bc78fd04a8115c60995e | commitdiff |
target/riscv: Add support for the new execption numbers
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu_bits.h | diffblobblamehistory | |
| target/riscv/cpu_helper.c | diffblobblamehistory | |
| target/riscv/csr.c | diffblobblamehistory |