target/riscv: Allow enabling the Hypervisor extension
commitc9eefe05a42d05d7a6dc49805f123579e5558d5d
authorAlistair Francis <alistair.francis@wdc.com>
Sat, 1 Feb 2020 01:03:11 +0000 (31 17:03 -0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Thu, 27 Feb 2020 21:46:34 +0000 (27 13:46 -0800)
tree37279fedf0b69d925880b6eca4dfb7b3abe2c35d
parente44b50b5b2e508fdd24915ab0e44ac49685e1de3
target/riscv: Allow enabling the Hypervisor extension

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
target/riscv/cpu.c
target/riscv/cpu.h