target/riscv: Emulate TIME CSRs for privileged mode
commitc695724868ce4049fd79c5a509880dbdf171e744
authorAnup Patel <anup.patel@wdc.com>
Sun, 2 Feb 2020 13:42:16 +0000 (2 19:12 +0530)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Thu, 27 Feb 2020 21:46:36 +0000 (27 13:46 -0800)
treee399f75e9a1aeb4f9c64dfa9a5e985413d5e8d24
parentacead54c78c7294612f529413673eb4286fb8b18
target/riscv: Emulate TIME CSRs for privileged mode

Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.

For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.

We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/csr.c