target/riscv: Add support for virtual interrupt setting
commit3ef10a098b0d3ebb02bf8e1325adc3b77af92f0b
authorAlistair Francis <alistair.francis@wdc.com>
Sat, 1 Feb 2020 01:02:23 +0000 (31 17:02 -0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Thu, 27 Feb 2020 21:45:39 +0000 (27 13:45 -0800)
tree29a9f33f64705c3ba6a2752f68ba6c4e9f1dd246
parenta2e9f57d06279220b1834eca2494e52adae121b8
target/riscv: Add support for virtual interrupt setting

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
target/riscv/cpu_helper.c