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MAINTAINERS: Add an entry for OpenSBI firmware
2020-07-14 Bin MengMAINTAINERS: Add an entry for OpenSBI firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: configure and turn on vector extension...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector compress instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector register gather instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector slide instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: floating-point scalar move instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer scalar move instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer extract instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector element index instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector iota instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: set-X-first mask bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vmfirst find-first-set mask bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask population count vmpopc
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask-register logical instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector wideing integer reduction instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: narrowing floating-point/integer type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: widening floating-point/integer type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point/integer type-convert...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point merge instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point classify instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point compare instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point sign-injection...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point min/max instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point square-root instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point fused...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point fused...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point multiply
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point add/subtract...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point add...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector narrowing fixed-point clip instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width scaling shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening saturating scaled multiply-add
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width fractional multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width averaging add and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width saturating add and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer merge and move instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer multiply-add...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer multiply instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer divide instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer min/max instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer comparison instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector narrowing integer right shift...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width bit shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector bitwise logical instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer add-with-carry / subtract...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer add and subtract
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer add and subtract
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector amo operations
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add fault-only-first unit stride load
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector index load and store instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector stride load and store instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add an internals.h header
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector configure instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: support vector extension csr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: implementation-defined constant parameters
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector extension field in CPURISCVState
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 Alistair Francishw/riscv: Allow 64 bit access to SiFive CLINT
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 Jessica Clarkeriscv: plic: Add a couple of mising sifive_plic_update...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 Jessica Clarkeriscv: plic: Honour source priorities
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Add a dummy DDR memory controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Sort the SoC memmap table entries
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Support different boot source per...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive: Change SiFive E/U CPU reset vector...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Mengtarget/riscv: Rename IBEX CPU init routine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Add a new property msel for MSEL...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Rename serial property get/set...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Add reset functionality
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_gpio: Do not blindly trigger output...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Hook a GPIO controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_gpio: Add a new 'ngpio' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_gpio: Clean up the codes
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Generate device tree node for OTP
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_u: Simplify the GEM IRQ connect code...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: opentitan: Remove the riscv_ prefix of the...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Menghw/riscv: sifive_e: Remove the riscv_ prefix of the...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Use a smaller guess size for no-MMU PMP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Connect the UART device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Connect the PLIC device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francishw/intc: Initial commit of lowRISC Ibex PLIC
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francishw/char: Initial commit of Ibex UART
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Fix the ROM size
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Implement checks for hfence
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Move the hfence instructions to the rvh...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Report errors validating 2nd-stage PTEs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Set access as data_load when validating...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Mengriscv: Keep the CPU init routine names consistent
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Mengriscv: Generalize CPU init routine for the imacu CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Mengriscv: Generalize CPU init routine for the gcsu CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Bin Mengriscv: Generalize CPU init routine for the base CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francissifive_e: Support the revB machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Ian Jiangriscv: Add helper to make NaN-boxing for FP register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francisriscv: Initial commit of OpenTitan machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Add the lowRISC Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Don't set PMP feature in the cpu init
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU