target/riscv: vector single-width integer multiply-add instructions
commit54df813a331d3badfb83604c36bef7cb1de4315a
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:25:09 +0000 (1 23:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (2 09:19 -0700)
tree23076ca654177e314f9352a984833ff7d535654a
parent97b1cba39967251ab78b9d52fd9a4c62bb42d428
target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-22-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvv.inc.c
target/riscv/vector_helper.c