| commit | ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 | |
| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | |
| Wed, 1 Jul 2020 15:24:49 +0000 (1 23:24 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 2 Jul 2020 16:19:32 +0000 (2 09:19 -0700) | ||
| tree | 4ec5715de24553e6f3a9c82e8e9e29586b4a267a | treesnapshot (tar.gz zip) |
| parent | 70b78d4e71494c90d2ccb40381336bc9b9a22f79 | commitdiff |
target/riscv: add vector extension field in CPURISCVState
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.h | diffblobblamehistory | |
| target/riscv/translate.c | diffblobblamehistory |