| commit | 354908cee1f7ff761b5fedbdb6376c378c10f941 | |
| author | Ian Jiang <ianjiang.ict@gmail.com> | |
| Tue, 28 Jan 2020 00:37:07 +0000 (28 08:37 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 19 Jun 2020 15:24:07 +0000 (19 08:24 -0700) | ||
| tree | 8c1a64811f91139c538ac9f80d1248fef51c9582 | treesnapshot (tar.gz zip) |
| parent | 4d285821c5055ed68a6f6b7693fd11a06a1aa426 | commitdiff |
riscv: Add helper to make NaN-boxing for FP register
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Message-Id: <20200128003707.17028-1-ianjiang.ict@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Message-Id: <20200128003707.17028-1-ianjiang.ict@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/insn_trans/trans_rvf.inc.c | diffblobblamehistory |