| commit | 32931383270e2ca8209267ca99f23f3c5f780982 | |
| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | |
| Wed, 1 Jul 2020 15:24:50 +0000 (1 23:24 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 2 Jul 2020 16:19:32 +0000 (2 09:19 -0700) | ||
| tree | e43e9d81617527a553c74cdd899cf977c1572186 | treesnapshot (tar.gz zip) |
| parent | ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 | commitdiff |
target/riscv: implementation-defined constant parameters
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-3-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-3-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory |