| commit | 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 23 Apr 2020 17:50:09 +0000 (23 10:50 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 3 Jun 2020 16:11:51 +0000 (3 09:11 -0700) | ||
| tree | 9ba62390cd163c7be8fae917cedeabeadf3d0160 | treesnapshot (tar.gz zip) |
| parent | ff832b77aa8ab454e092fb73b61821e56218e8a5 | commitdiff |
target/riscv: Add the lowRISC Ibex CPU
Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.
For more details on lowRISC see here:
https://github.com/lowRISC/ibex
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.
For more details on lowRISC see here:
https://github.com/lowRISC/ibex
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory |