Public Git Hosting - qemu/ar7.git/search

2020-06-19	Alistair Francis	target/riscv: Move the hfence instructions to the rvh... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Report errors validating 2nd-stage PTEs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Set access as data_load when validating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	sifive_e: Support the revB machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv: Initial commit of OpenTitan machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Add the lowRISC Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Don't set PMP feature in the cpu init Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Disable the MMU correctly Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Don't overwrite the reset vector Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv/boot: Add a missing header include Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv: sifive_e: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	docs: deprecated: Update the -bios documentation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Drop support for ISA spec version 1.09.1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Remove the deprecated CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	hw/riscv: spike: Remove deprecated ISA specific machines Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv: AND stage-1 and stage-2 protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv: Don't use stage-2 PTE lookup protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv/sifive_u: Add a serial property to the sifive_u SoC Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv/sifive_u: Fix up file ordering Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-30	Alistair Francis	linux-user: Support futex_time64 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user/riscv: Update the syscall_nr's to the 5... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user/syscall: Add support for clock_gettime64... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user: Protect more syscalls Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-17	Alistair Francis	target/riscv: Correctly implement TSR trap Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Allow enabling the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the MSTATUS_MPV_ISSET helper macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for the 32-bit MSTATUSH CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Set htval and mtval2 on execptions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Raise the new execptions when 2nd stage... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Implement second stage MMU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Allow specifying MMU stage Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Respect MPRV and SPRV for floating point ops Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Mark both sstatus and msstatus_hs as... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Disable guest FP support based on virtual... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Only set TB flags with FP status if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Remove the hret instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor trap return support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add hypvervisor trap support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Generate illegal instruction on WFI when V=1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/ricsv: Flush the TLB on virtulisation mode changes Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for virtual interrupt setting Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Extend the SIP CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Extend the MIE CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Set VS bits in mideleg for Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add virtual register swapping function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor machine CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor virtual CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor CSR access functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Dump Hypervisor registers if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Print priv and virt in disas log Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Fix CSR perm checking for HS mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the force HS exception mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the virtulisation mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Rename the H irqs to VS irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for the new execption numbers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the Hypervisor CSRs to CPUState Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Convert MIP CSR to target_ulong Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/arm: Add the Netduino Plus 2 Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/arm: Add the STM32F4xx SoC Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/misc: Add the STM32F4xx EXTI device Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/misc: Add the STM32F4xx Sysconfig device Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	riscv/virt: Increase flash size Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	opensbi: Upgrade from v0.4 to v0.5 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	target/riscv: Remove atomic accesses to MIP CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/boot: Fix possible memory leak Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Jump to pflash if specified Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Add the PFlash CFI01 device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add the start-in-flash property Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add QSPI memory region Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add L2-LIM cache memory Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Fix mstatus dirty mask Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Update the Hypervisor CSRs to v0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Create function to test if FP is enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	riscv: plic: Remove unused interrupt functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-26	Alistair Francis	riscv/boot: Fixup the RISC-V firmware warning Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	hw/riscv: Load OpenSBI as the default firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	roms: Add OpenSBI version 0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-09	Alistair Francis	tcg/riscv: Fix RISC-VH host build failure Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Extend the kernel loading support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Add support for loading a firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Split out the boot functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add support for disabling/enabling Counters Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Remove user version information Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Require either I or E base extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Set privledge spec 1.11.0 as default Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add the mcountinhibit CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Add the privledge spec version 1.11.0 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Restructure deprecatd CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Allow setting ISA extensions via CPU... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the HGATP register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the HSTATUS register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add Hypervisor CSR macros Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Allow setting mstatus virtulisation bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the MPV and MTL mstatus bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
next

AR7 emulation for QEMU

RSS Atom