target/riscv: Add support for disabling/enabling Counters
commit0a13a5b856ebb59dec6d165b87a0ba0e1e2dd952
authorAlistair Francis <alistair.francis@wdc.com>
Tue, 18 Jun 2019 01:31:22 +0000 (17 18:31 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 25 Jun 2019 10:05:41 +0000 (25 03:05 -0700)
tree829043603c8ad0567ca3e14e6f7a7f88ca9f6901
parentc9a73910c34a2147bcf6a3b5194d27abb19c2e54
target/riscv: Add support for disabling/enabling Counters

Add support for disabling/enabling the "Counters" extension.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/csr.c