riscv: AND stage-1 and stage-2 protection flags
commit8f67cd6db7375f9133d900b13b300931fbc2e1d8
authorAlistair Francis <alistair.francis@wdc.com>
Thu, 26 Mar 2020 22:44:09 +0000 (26 15:44 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 29 Apr 2020 20:16:37 +0000 (29 13:16 -0700)
tree0d676167fc5b6b7c973021a1d6dfc43fd02005cc
parent384728905441279e54fa3d714b11bf1b1bcbfd27
riscv: AND stage-1 and stage-2 protection flags

Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Anup Patel <anup@brainfault.org>
Message-id: 846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com
Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com>
target/riscv/cpu_helper.c