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target/riscv: Move the hfence instructions to the rvh decode
2020-06-19
Alistai
r
F
rancis
target/riscv: Move th
e
hfence i
n
structions to
t
he
r
vh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
n
c
i
s
target/riscv: Report errors valid
a
ting 2nd-stage
PTE
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir F
r
a
ncis
ta
r
get/riscv: Set acc
e
ss as data_load when validati
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
ista
i
r Francis
si
f
ive_e: Support th
e
revB mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franc
i
s
ris
c
v
: Ini
t
ial commit of Ope
n
Titan
m
a
chi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
sta
i
r Francis
target/riscv: Add the lowRI
S
C Ibe
x
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
i
stair
Fra
n
cis
t
arg
e
t/riscv: Don't set PMP fe
a
ture in the cpu i
n
it
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
F
rancis
target/ris
c
v
:
Disable the MMU
correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Francis
target
/
ris
c
v:
Don't ov
e
rwrite
the re
s
et vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv/
b
oo
t
: Add a missing header include
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv: sifiv
e
_e: Manually define the mac
h
ine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
F
r
ancis
docs: deprecated: Upd
a
te the -bi
o
s
do
c
umentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
t
arget/riscv: D
r
o
p
support for ISA spec versi
o
n 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listair Fra
n
cis
t
a
r
g
et/riscv
:
R
emove t
h
e
d
eprecated
CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
tair Francis
hw/riscv:
s
pike: Remove deprecated ISA sp
e
ci
f
ic ma
c
hines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alista
i
r Franci
s
riscv: AND stage-1 and
s
tage-
2
p
r
otection
f
lags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair
F
rancis
ris
c
v
: Don't
u
se stage-2 PTE l
o
oku
p
p
r
ote
c
t
i
o
n fla
g
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alis
t
air Francis
r
i
sc
v
/sifive_
u
: Ad
d
a serial proper
t
y to the sifive_u
S
oC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Ali
s
t
a
ir Franci
s
risc
v
/sifive_u: Fix
u
p
fil
e
o
r
derin
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Ali
s
tair Fran
c
is
linux-
u
ser: Support futex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair
Francis
linux-user/riscv: Up
d
at
e
the sy
s
call_nr's t
o
th
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Fra
n
cis
linux-user/
s
yscal
l
: Add
sup
p
ort for cloc
k
_getti
m
e64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
linux-user: Protec
t
more s
y
scalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alistair Franci
s
tar
g
et/riscv: Correc
t
ly im
p
lement
T
SR t
r
a
p
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
t
a
ir Francis
ta
r
ge
t
/riscv
:
Allo
w
e
n
a
b
lin
g
the H
y
pervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
t
arget/riscv: Add the MSTATUS_MPV_ISSET helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Francis
t
arget/riscv:
A
dd
su
p
port for the 32
-
bit MST
A
T
USH C
S
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
tar
g
e
t/risc
v
: Set ht
v
al an
d
mtval2 on execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
Fra
n
cis
target/riscv
:
R
ais
e
the new execptio
n
s when 2nd
stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
ranc
i
s
t
arget/riscv: Imp
l
e
m
e
nt second stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
i
r
Francis
target/r
i
scv: Allow s
p
ecifyi
n
g MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/
r
i
scv: Respect
MP
R
V and SPRV fo
r
floating point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Mark both ss
t
atus and msst
a
t
us_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
Fra
n
c
i
s
target/risc
v
: Di
s
able guest FP supp
o
rt
b
a
se
d
on virtual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/ris
c
v:
O
n
l
y set TB f
l
ags wi
t
h F
P
statu
s
if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair
Francis
target
/
ris
c
v
: Remo
v
e
the
hret
i
n
s
tru
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/r
i
s
c
v: Add hfe
n
ce ins
t
ructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
ta
r
g
et/
r
iscv:
A
dd
H
y
pervisor t
r
a
p
return su
p
po
r
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
target/riscv: Add hypvervi
s
or trap
s
upport
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
i
r Fra
n
c
is
target/riscv: Gen
e
rate i
l
legal instruction
o
n WFI when V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Franc
i
s
target/ricsv: Flush the
T
LB o
n
virtulisation
m
o
d
e
changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Fr
a
ncis
target/riscv: Add support fo
r
virtua
l
interru
p
t
s
e
t
tin
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
ran
c
is
targ
e
t/ri
s
cv: Extend the SIP CS
R
to support
v
i
rtulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
target/riscv:
Extend the MIE CSR to supp
o
rt virtuli
s
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
ista
i
r Francis
targe
t
/riscv
:
Set VS
b
its in
mideleg for
Hyp exten
s
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
t
arget/ris
c
v
:
Add
virtual
r
egis
t
er sw
a
pping f
u
nction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targe
t
/r
i
scv: A
d
d Hyper
v
isor m
a
chi
n
e CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
st
a
ir Fran
c
is
target/riscv: Add Hypervisor virtu
a
l CSRs a
c
cesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
a
i
r
Fra
n
ci
s
target/ri
s
cv: A
d
d Hypervisor
CSR access f
u
nctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
Francis
tar
g
et/riscv:
Dump Hypervisor registers if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
t
arget/riscv: Print priv a
n
d v
i
rt in
d
isas lo
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
targe
t
/riscv: Fix
C
SR perm check
i
ng for HS mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Francis
t
a
rget
/
risc
v
:
A
d
d
the force HS exception
m
ode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
F
rancis
targe
t
/riscv: Ad
d
the vir
t
u
lisat
i
on mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target
/
r
i
scv: Rename the H irq
s
to
V
S ir
q
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair Franci
s
target/ri
s
cv:
Add support for
t
he
new
e
xec
p
tio
n
numbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
t
a
rge
t
/
r
iscv: A
d
d the Hyp
e
r
v
isor CSRs to CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair
Francis
target/ris
c
v: Add t
h
e Hypervi
s
or ex
t
ension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair F
r
ancis
target/ri
s
cv: Convert MIP CSR to targe
t
_u
l
on
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw/arm: Add the N
e
tduin
o
Plus
2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Al
i
stair Francis
hw/arm:
Ad
d
t
he STM3
2
F4xx
S
o
C
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistai
r
F
r
ancis
hw/misc: Ad
d
the
S
TM32F4xx EX
T
I
d
evice
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alista
i
r Francis
hw/misc:
Add the
STM32F
4
xx
Sysconfig dev
i
c
e
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
A
listair
Francis
r
i
s
c
v/vir
t
: In
c
reas
e
fla
s
h size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
l
istair Francis
op
e
ns
b
i: U
p
gra
d
e
from v0
.
4 to v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
Alistai
r
F
r
a
ncis
tar
g
et/riscv: Re
m
ove
a
t
omi
c
accesses
to MIP CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
l
ista
i
r Francis
ri
s
cv/boot: Fix
p
oss
i
b
l
e memory leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
l
ist
a
ir Fr
a
n
cis
ri
s
cv/virt: Jump to pflash if s
p
ecif
i
ed
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Fr
a
n
c
is
riscv/virt: Ad
d
t
h
e PFlash CFI01 devic
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Fran
c
is
r
i
sc
v
/v
i
rt: Manu
a
ll
y
de
f
ine
t
h
e
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alis
t
air Franc
i
s
riscv/
s
ifiv
e
_u: Add the start
-
in-flash property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Francis
ris
c
v/sif
i
ve_u:
Manually d
e
fine the m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
l
istair Francis
r
i
scv/s
i
five_
u
: A
d
d QSPI
m
em
o
r
y
region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alist
a
ir Fra
n
cis
ris
c
v/sifive_u
:
Add L2-LIM cache memory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Fra
n
cis
t
arget/ris
c
v: Us
e
T
B
_
F
LA
G
S_MST
A
TU
S
_FS for floating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alista
i
r Francis
target/riscv: Fi
x
mstatus dirty mask
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2019-09-17
Alistair
F
rancis
ta
r
g
et/ris
c
v: Update
the Hyperv
i
sor CSRs to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-09-17
Alistair Francis
t
a
r
g
e
t/ris
c
v:
C
reate function to test
if FP is
e
nabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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commitdiff
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2019-09-17
Alistair
F
ran
c
i
s
ris
c
v: plic: Remove unused int
e
rrupt functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-07-26
Alistair F
r
ancis
riscv/boot: Fixup the RISC-V
fi
r
m
wa
r
e warning
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-07-18
A
l
i
s
tai
r
F
ran
c
is
hw/riscv:
L
oad OpenS
B
I as the default fir
m
ware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-18
Alist
a
ir
F
rancis
r
oms: Add OpenSBI version 0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-07-09
A
l
istair
F
r
ancis
tc
g
/ris
c
v: Fix
RISC-VH host b
u
ild
failur
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2019-06-27
Alist
a
ir
F
rancis
hw/riscv: Exte
n
d t
h
e kernel loading sup
p
ort
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-06-27
Alista
i
r
F
r
ancis
hw/riscv: Add support for loa
d
ing a
firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
Alist
a
ir F
r
anc
i
s
hw/riscv: Spl
i
t out
the bo
o
t functio
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-06-25
Alistair Francis
target/r
i
scv:
A
dd
s
u
pport for dis
a
bling/enabling Coun
t
ers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-06-25
Alistair Fra
n
cis
target/riscv: Re
m
ove user version information
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-06-25
Al
i
stair
Francis
target/riscv
:
Requir
e
ei
t
h
er
I
or E base extens
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alista
i
r Francis
q
emu-deprec
a
ted
.
texi: Deprecate the R
I
SC-V privledge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alistair Francis
target/riscv: Set
p
ri
v
ledge spec
1
.
11
.
0
as de
f
ault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
A
l
ista
i
r Francis
target/r
i
scv:
Add the
m
c
o
unt
i
nhibit CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-24
Al
i
sta
i
r Francis
target/riscv: Add the pr
i
vledg
e
spe
c
version 1
.
11
.
0
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-24
Alista
i
r Francis
tar
g
et/riscv: Restructure de
p
reca
t
d CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-24
Alistair Francis
tar
g
et/riscv:
Allow se
t
t
i
n
g
ISA
extensio
n
s via
CPU
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Al
i
s
t
a
ir Francis
t
arget/r
i
s
cv: Add the HGATP register mas
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Alist
a
ir Fra
n
cis
targe
t
/ris
c
v: Add the HSTATUS
r
egister m
a
sks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
A
l
is
t
air Fr
a
ncis
target/riscv: A
d
d Hyp
e
r
v
is
o
r
CSR macr
o
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Ali
s
t
a
ir Fra
n
c
i
s
t
a
rg
e
t/riscv: Allow setting
m
st
a
tus virtulisation bits
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-05-24
Alistair Fr
a
nci
s
t
a
r
g
e
t
/risc
v
: Add the
MPV and MTL mstatus bits
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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