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tests/acceptance: Skip slow quanta-gsj U-boot+Linux test
2020-08-25
A
listair Franc
i
s
t
arg
e
t/
r
iscv: Supp
o
rt the V
i
r
t
u
a
l Instru
c
ti
o
n
fa
u
lt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair F
r
ancis
t
a
rget/riscv:
R
eturn
t
h
e e
x
cept
i
on fro
m
i
n
valid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istai
r
F
r
ancis
target/riscv: Support the v0
.
6 Hypervisor extension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air Fra
n
cis
ta
r
g
et/riscv: Only support li
t
tle end
i
an
guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/
r
iscv: Only
s
u
p
port a single VSXL
l
e
ngth
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair F
r
ancis
t
arget/riscv
:
U
p
d
ate the CSRs to the
v0
.
6 Hyp extensio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Fra
n
ci
s
t
a
rget
/
ris
c
v: Updat
e
the Hypervisor trap retu
r
n/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stair
Francis
t
a
rget/
r
iscv:
Fix the interr
u
pt cause c
o
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Francis
target/riscv:
C
onvert MST
A
TUS M
T
L
to GV
A
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv:
D
on't allow
guest to
w
r
i
te to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
Francis
t
arget/riscv: Do two-stage lookups o
n
hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
t
a
rget/riscv
:
Allow generating hl
v
/
h
l
v
x/hsv instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
ta
r
get/riscv: Allow setti
n
g
a
t
w
o-stage
l
ookup
in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alis
t
air Francis
hw/intc: ibex_
p
lic: Honour so
u
rce priorities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alis
t
ai
r
Fran
c
is
hw/intc: ib
e
x_pli
c
: Don't allow
rep
e
at i
n
t
e
r
r
upts o
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc:
i
b
e
x_plic: Update the pending irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alist
a
ir Francis
hw/sd/pl181: Replace fprintf(stde
r
r, "*\n") with erro
r
_repor
t
()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Al
i
s
tair Francis
hw/c
h
ar: Convert th
e
Ibex UA
R
T to us
e
the register
f
ields
A
PI
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
A
l
istair Francis
hw/c
h
ar: Conve
r
t the Ibex UART
to use the
qd
e
v C
l
ock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Francis
hw/riscv: Allow 64 bit a
c
cess to
SiFive CLI
N
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
ta
r
get/r
i
scv: Use
a smal
l
er guess size
f
or no-MMU
P
MP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
ri
s
cv/opent
i
ta
n
: Connect
the UART
devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair F
r
a
n
ci
s
ris
c
v/opentitan: Connect the PL
I
C device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/intc: Initial
c
o
m
mit o
f
lowRISC Ibex
PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/char: Initial commit
o
f I
b
ex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Franci
s
r
iscv/o
p
entitan: Fix the ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
istair Francis
target/riscv: Imple
m
ent check
s
for hfenc
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
targe
t
/riscv: M
o
v
e
th
e
hfence ins
t
r
u
ct
i
o
n
s
t
o
the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tai
r
Fra
n
cis
target/
r
iscv: Report errors val
i
dati
n
g 2nd-stage
P
TEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair Francis
tar
g
et/riscv: Se
t
access as dat
a
_load when validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Fr
a
ncis
s
ifive_e:
S
up
p
ort the
r
e
vB mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistai
r
Franci
s
riscv: Initial com
m
it of
O
pe
n
Tit
a
n mac
h
in
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fr
a
ncis
t
a
r
get/
r
isc
v
: Add
the lowRISC I
b
ex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franc
i
s
t
a
r
g
et/riscv: Don't set PMP feat
u
re
i
n
the cpu init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alis
t
ai
r
Fra
n
cis
target/riscv: D
i
s
a
ble the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listair Francis
target/riscv: Don't
overwrite the re
s
et vec
t
or
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listai
r
Fr
a
n
c
is
r
i
s
c
v
/boot: Add
a
missing header include
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Francis
ri
s
cv: sifive_e: Manually define the machin
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
lis
t
air
F
rancis
docs: depreca
t
ed: Update the -bios d
o
c
umentat
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Fra
n
cis
target/ri
s
cv: Drop support for ISA spec ver
s
ion 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listair Francis
ta
r
g
et/ris
c
v: Remove the de
p
recated
CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
hw/
r
i
scv: spike
:
Remove d
e
pre
c
ated IS
A
specific mac
h
ines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv:
AND sta
g
e-1
a
nd stag
e
-
2
prot
e
c
t
ion flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
l
i
stai
r
F
ranc
i
s
riscv: Don't use
s
tage-
2
PTE lo
o
kup protection f
l
a
gs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
listair F
r
ancis
riscv/sifiv
e
_u: A
d
d a se
r
ial p
r
operty to the sifive_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv/si
f
iv
e
_u: F
i
x
up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alistair Francis
linux-user: S
u
pport futex_time6
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
l
i
n
ux-u
s
er/riscv: Update th
e
syscall_nr's to the
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
A
lista
i
r Fra
n
cis
l
inux-us
e
r/sysca
l
l
: Add supp
o
rt for clock_get
t
ime6
4
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
linux-user:
P
rotect
m
ore syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Ali
s
tair Francis
target/
r
isc
v
: Cor
r
ectly implement TSR trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
lis
t
air Francis
target/riscv: Allow enabling the Hypervisor ex
t
ension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair Francis
target/
r
i
sc
v
: Add the MSTATUS_MPV_ISSET helper
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air
F
ranc
i
s
tar
g
et
/
riscv: Add support for the
3
2-bit
M
STA
T
USH
CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
s
t
air Francis
t
a
rget/
r
iscv: Set htval and mtval2 on execpt
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
targe
t
/riscv
:
Ra
i
se th
e
new execpti
o
ns
w
hen 2nd sta
g
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Fr
a
ncis
t
a
r
get/riscv: Im
p
l
e
ment second stage
M
MU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair F
r
an
c
is
target/riscv:
A
llow
s
p
ecifying
M
M
U stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
is
target/riscv: Res
p
ect MPRV
a
nd
SP
R
V
for floating point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair F
r
a
ncis
target/riscv: Mark bot
h
sstatus and ms
s
ta
t
u
s
_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
t
arget/r
i
scv:
Disabl
e
guest FP support base
d
o
n
vi
r
tual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
rancis
target/ris
c
v: Only set T
B
f
la
g
s w
i
t
h
FP st
a
tu
s
if e
n
abled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Franci
s
target/ri
s
cv: Remove t
h
e hret instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
ran
c
i
s
t
ar
g
e
t/r
i
scv
:
Add hfe
n
ce
i
nstruction
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair
Franci
s
target/ris
c
v: Add
Hyper
v
isor trap retu
r
n support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
s
t
a
i
r Francis
target/
r
i
s
cv: Add hypverv
i
sor tr
a
p
s
uppo
r
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Franci
s
t
arget/riscv:
G
enerat
e
il
l
eg
a
l i
n
s
t
ruction o
n
WFI wh
e
n V
=
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Franc
i
s
tar
g
et/ricsv:
Flush the TLB on virt
u
l
i
s
at
i
on mo
d
e changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
t
a
rge
t
/riscv: A
d
d suppo
r
t for virtual interrup
t
setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
ta
r
get/riscv: Extend
th
e
SIP C
S
R to su
p
port vi
r
tulisatio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
r
a
ncis
t
arget/ris
c
v
:
E
xtend
t
he MIE
C
SR to suppo
r
t virtulisat
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
s
tair
F
rancis
target/riscv
:
Set
VS bits i
n
mideleg for Hyp exte
n
sion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Francis
ta
r
g
e
t
/riscv: Add virtual register swapping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
targe
t
/
riscv: Add H
y
perv
i
s
o
r machine CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistai
r
F
r
ancis
targ
e
t/r
i
scv: A
d
d Hypervisor virtual CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-02-27
Alistai
r
Francis
t
a
rget/ri
s
cv
:
Add Hypervisor CSR
a
ccess fu
n
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fr
a
ncis
target/riscv
:
Dump Hypervisor registers if ena
b
led
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-02-27
Ali
s
tair Francis
target/riscv: Print priv and virt in d
i
sas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-02-27
Alistair Fra
n
cis
target/ris
c
v: Fix CSR per
m
chec
k
ing for HS mo
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-02-27
Alis
t
air Fra
n
cis
target/riscv: Add the
for
c
e H
S
exc
e
p
t
ion mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Fra
n
c
is
target/ris
c
v
: Add the virtulisati
o
n mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
l
istair Francis
target
/
riscv: Rename the H irq
s
to VS irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Alistair Franc
i
s
target/riscv: Add
suppor
t
for t
h
e new e
x
ecption num
b
ers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
listair Francis
targe
t
/
ri
s
c
v
:
A
dd the
H
y
p
ervis
o
r CSRs to CPUStat
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Ali
s
t
a
ir
F
ranci
s
t
a
rget/
r
i
s
c
v: A
d
d the Hyper
v
i
s
or extensio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
l
istai
r
F
r
ancis
target/riscv: Con
v
er
t
MIP CSR t
o
targe
t
_ul
o
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-01-17
Ali
s
t
ai
r
Francis
h
w/arm:
A
dd the Netduino
Plus 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
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tree
2020-01-17
Alistair Fr
a
ncis
hw/ar
m
:
Add the STM32F4xx SoC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
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tree
2020-01-17
Alista
i
r
F
r
ancis
hw/m
i
sc: Add the ST
M
32F4xx EXTI de
v
ice
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
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2020-01-17
Alistair Fran
c
is
h
w
/misc
:
A
d
d
the STM32F4xx Sy
s
c
onfig device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
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commitdiff
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tree
2019-11-14
Al
i
stair Fra
n
cis
risc
v
/virt: Inc
r
e
as
e
flas
h
size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-11-14
Alistair Fr
a
ncis
opensbi: Upgrade fro
m
v0
.
4 t
o
v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-11-14
A
listair Franc
i
s
tar
g
et/riscv: Remove ato
m
ic accesses to
M
IP C
S
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
Al
i
st
a
ir
F
rancis
r
i
scv/boo
t
: Fi
x
possible memory leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
A
listair Francis
riscv/v
i
rt: Jump
to pfla
s
h if
s
pe
c
if
i
ed
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
Alista
i
r
F
r
an
c
is
riscv/virt: Add
the P
F
la
s
h
CFI01 devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
A
listair
F
ranci
s
ris
c
v/virt: Manu
a
lly define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
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tree
2019-10-28
Al
i
stair Francis
riscv/sifive
_
u
:
Add the
st
a
rt-in-flas
h
property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
Alistair Francis
ri
s
c
v
/s
i
five_
u
: Manua
l
ly
d
efine the ma
c
hine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
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2019-10-28
A
l
istair Fran
c
is
riscv/si
f
ive_u
:
Add
QSP
I
m
emory region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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