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hw/riscv: sifive_u: Add reset functionality
2020-06-19
Alistair Fra
n
c
i
s
targe
t
/
r
iscv:
U
se
a
s
m
aller guess size
for no-MMU P
M
P
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Francis
riscv/opentitan: Con
n
ect
t
he UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
istair Francis
riscv/opentitan: Con
n
ect the PLIC dev
i
ce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw
/
in
t
c: Initial commit of lowR
I
S
C
Ibex
P
L
I
C
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/char: I
n
itial
c
ommit
of Ibex
U
ART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair
Francis
riscv/opentitan: Fix the ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Francis
tar
g
et/riscv: Imp
l
ement c
h
e
c
ks for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair
Francis
tar
g
et/risc
v
: M
o
ve the h
f
ence
in
s
tructions to the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
Francis
target/riscv: Report
e
rrors
vali
d
at
i
ng 2nd-stag
e
PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
istair Francis
target/ri
s
cv: Set access as
data_load
when validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Francis
s
i
five_e: S
u
pport
t
he revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Francis
riscv
:
Init
i
al comm
i
t
of OpenTitan
mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listair Francis
target/riscv: Add th
e
lowRI
S
C Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listair Francis
target/risc
v
: D
o
n't set PMP fea
t
ure in t
h
e cpu i
n
it
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
target/riscv: D
i
sa
b
le t
h
e MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
t
arg
e
t/r
i
scv:
Don't overwrit
e
t
he reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Francis
riscv/boo
t
:
A
dd a missin
g
head
e
r
i
nclude
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair
F
ra
n
c
i
s
riscv:
s
i
f
ive
_
e: Manuall
y
define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
ancis
docs: depreca
t
ed: Update the -bios documentatio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
ista
i
r F
r
ancis
target/ri
s
cv: D
r
op support f
o
r ISA sp
e
c
version 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
a
ncis
targ
e
t/riscv: Remove the deprec
a
t
e
d CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
hw/riscv: spike: R
e
move deprecated ISA spec
i
fic mach
i
nes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
risc
v
: AND stage-
1
and sta
g
e-2 p
r
ote
c
t
i
o
n
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
l
is
t
air Fr
a
ncis
riscv: Don't use stage-2 PTE lookup protect
i
on fl
a
gs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv/sifi
v
e_u: A
d
d
a seria
l
pr
o
pert
y
to the sifi
v
e_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Franc
i
s
riscv/sifive_u: F
i
x
up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alist
a
ir Francis
linux-
u
ser
:
Support
futex
_
time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alis
t
air Fra
n
cis
l
inux-u
s
er/ri
s
c
v: U
p
date t
h
e sysc
a
ll_
n
r
'
s to the 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
A
l
i
stair Fran
c
is
lin
u
x-
u
s
er/sys
c
all: Add support for clock_
g
etti
m
e64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
A
l
istair
F
rancis
linux-us
e
r: P
r
otect mor
e
syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alist
a
ir
F
rancis
targ
e
t/riscv:
C
o
rre
c
tly impl
e
ment TS
R
t
rap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/r
i
scv:
Allow enabling
t
he
Hype
r
visor e
x
te
n
sion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istai
r
F
rancis
targ
e
t/riscv:
Add the MSTAT
U
S_MPV
_
ISSET
helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
F
r
a
n
cis
target/r
i
scv: Add support for the 32-b
i
t
MSTA
T
USH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
tar
g
et/r
i
scv: Set htval
a
nd mtva
l
2
o
n exec
p
ti
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franci
s
target
/
riscv
:
Raise the
n
ew execptions when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Fran
c
i
s
tar
g
et/r
i
scv: Implement second st
a
ge MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targe
t
/ri
s
cv: Allow speci
f
ying M
M
U stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
s
t
a
ir Francis
target/riscv: Respect MPRV and SPR
V
for fl
o
a
t
ing p
o
int ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
lista
i
r Franci
s
target/riscv: Mark both ss
t
atus and
msstatus_hs a
s
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targe
t
/
ri
s
cv:
D
i
sable
guest FP support based on vi
r
tual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Francis
target
/
riscv: Only
set TB
f
lags wit
h
FP status if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
t
a
rget/ri
s
cv: Remove t
h
e hret instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targ
e
t/r
i
scv: Add
h
fence i
n
stru
c
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
is
targ
e
t/riscv: A
d
d Hy
p
ervisor tr
a
p retu
r
n support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
F
r
ancis
t
arge
t
/
riscv:
Add hyp
v
ervisor trap support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/risc
v
: Generate illegal in
s
tru
c
tion on WF
I
w
hen V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/ricsv:
Fl
u
sh the TLB on virtulisation mod
e
changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
ist
a
ir Francis
target/riscv: Add support
f
o
r virtual interrupt setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
a
ir Fran
c
is
t
a
rget/riscv: Exte
n
d
t
he
SIP
C
SR to sup
p
ort v
i
rtulisati
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
ranc
i
s
target
/
risc
v
: Exte
n
d the
M
IE CSR to support virtuli
s
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair
F
rancis
target/risc
v
: Set VS bits in
mideleg for Hyp
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: A
d
d
v
i
r
t
ual regi
s
ter s
w
apping fu
n
ction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
stair Francis
targ
e
t/riscv: Add H
y
pervisor machine CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
target/riscv: Add Hypervisor vi
r
tual
C
SRs
a
ccesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air
F
ra
n
cis
target/r
i
scv: Add H
y
pervisor
C
SR access functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
target/ri
s
cv: D
u
m
p
H
y
p
ervisor r
e
gisters if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Francis
ta
r
get/riscv: Print priv and virt in disas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
s
t
air Francis
target
/
riscv: Fix C
S
R perm c
h
eck
i
ng
for HS mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Add the
fo
r
ce
H
S exception mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
is
t
ai
r
Franc
i
s
tar
g
et/
r
iscv: Add the virtulisat
i
on mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Francis
targe
t
/ris
c
v: Ren
a
me the H irqs to V
S
irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Add support
f
or the new execption numbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
t
arget/riscv: Add the Hype
r
visor CSRs to
C
PUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franci
s
target/riscv: A
d
d
the Hyp
e
rvisor extensi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
ta
r
get/r
i
s
c
v: Convert
M
IP CSR to target
_
ulong
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
Alist
a
ir Francis
hw/arm
:
Add
the Netdu
i
no Plus 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw/arm: Add t
h
e STM32F4xx SoC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alist
a
ir Francis
hw/
m
is
c
: Add the STM32F4xx EXTI dev
i
c
e
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alis
t
air Francis
hw/misc: Add the S
T
M32
F
4xx Sysconfig device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
Alis
t
air Francis
riscv/virt:
Increa
s
e flash size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Fr
a
nc
i
s
ope
n
sbi: Upgrade
from v0
.
4 to
v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Francis
targe
t
/riscv: Remove
atomic a
c
cesses t
o
M
IP CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Francis
riscv/b
o
ot
:
Fix poss
i
ble
memory leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
riscv/
v
irt: Jump
to pflash if specified
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
stair Francis
riscv/virt: Add the
PFlas
h
CFI01 device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Francis
riscv
/
virt: Manually define the machin
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alista
i
r F
r
anc
i
s
riscv/sifive_u: Add t
h
e star
t
-in-flash
p
r
o
perty
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Fr
a
ncis
riscv/sif
i
ve_
u
: Manually def
i
ne the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
A
lista
i
r Francis
riscv/sifive_u: Ad
d
QSPI memory reg
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
Alistair Francis
riscv/sifive_u:
Ad
d
L2-LIM
c
ache memory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alis
t
air Fra
n
cis
target/ris
c
v: Use TB_FLAGS
_
MSTA
T
US_FS for floating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Ali
s
tair Francis
target/ri
s
cv:
Fix mstatus di
r
ty mask
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alistair Franci
s
target/riscv
:
Update
the Hyperv
i
sor CSRs to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
A
listair Fr
a
ncis
t
arget/r
i
scv:
C
reate function to t
e
s
t if
FP i
s
e
n
abl
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alistair Franci
s
riscv: plic
:
Remove unused
i
nter
r
u
pt
f
uncti
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-26
Alis
t
air Fran
c
is
riscv/boot: Fixup t
h
e RISC-V f
i
rmware
w
arn
i
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-07-18
Alistair Francis
hw/riscv: Load
O
p
e
nSBI as the
defau
l
t fi
r
mware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-18
Alista
i
r F
r
ancis
roms: Add O
p
enSBI
v
ersion 0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-09
A
l
istair Francis
tcg/riscv: F
i
x RISC-V
H
host build f
a
ilure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-27
Al
i
stair Francis
hw/riscv: Ex
t
en
d
t
h
e
kerne
l
l
oad
i
ng support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
Alistai
r
F
r
ancis
hw/riscv: A
d
d sup
p
ort for
l
oading
a fir
m
ware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
A
l
istair Francis
hw/risc
v
: Spl
i
t out the
boo
t
functi
o
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
A
listair Fran
c
is
target/riscv: Add support fo
r
d
i
sablin
g
/
e
n
abling
Counters
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alista
i
r
F
rancis
t
ar
g
et/riscv: Re
m
ove
u
ser version
i
nform
a
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-06-25
Alistair
Franci
s
t
a
rget
/
ri
s
c
v
: Require either I or E ba
s
e
e
xtension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alistai
r
Francis
qemu-deprecated
.
t
exi:
D
epreca
t
e the RISC-V pr
i
v
ledge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alistair F
r
an
c
i
s
targ
e
t/riscv: Se
t
privledge
s
pec 1
.
11
.
0 as default
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
A
list
a
ir Fr
a
nc
i
s
t
a
rget/riscv: A
d
d the mcountinhibit CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-24
Ali
s
t
air Fran
c
is
t
a
r
get/riscv: Add the privledge spec version 1
.
11
.
0
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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