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hw/riscv: spike: Change the default bios to use generic platform image
2020-08-22 Bin Menghw/riscv: spike: Change the default bios to use generic...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menghw/riscv: Use pre-built bios image of generic platform...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengroms/Makefile: Build the generic platform for RISC...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengroms/opensbi: Upgrade from v0.7 to v0.8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Mengconfigure: Create symbolic links for pc-bios/*.elf...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Hou Weiyingriscv: Fix bug in setting pmpcfg CSR for RISCV64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Bin Menghw/riscv: sifive_u: Add a dummy L2 cache controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 LIU Zhiweitarget/riscv: check before allocating TCG temps
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 LIU Zhiweitarget/riscv: Clean up fmv.w.x
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Check nanboxed inputs in trans_rvf.inc.c
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Check nanboxed inputs to fp helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Generate nanboxed results from trans_rvf...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-08-22 Richard Hendersontarget/riscv: Generate nanboxed results from fp helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-22 Zong Litarget/riscv: Fix the range of pmpcfg of CSR funcion...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-22 Bin Menghw/riscv: sifive_e: Correct debug block size
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-22 LIU Zhiweitarget/riscv: fix vector index load/store constraints
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-22 LIU Zhiweitarget/riscv: Quiet Coverity complains about vamo*
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-22 Jessica Clarkegoldfish_rtc: Fix non-atomic read behaviour of TIME_LOW...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Alexandre Mergnattarget/riscv: Fix pmp NA4 implementation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Liao Pingfangtcg/riscv: Remove superfluous breaks
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Alistair Francishw/char: Convert the Ibex UART to use the registerfields API
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
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2020-07-14 Alistair Francishw/char: Convert the Ibex UART to use the qdev Clock...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...59ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
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2020-07-14 Frank Changtarget/riscv: fix vill bit index in vtype register
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Frank Changtarget/riscv: fix return value of do_opivx_widen()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Frank Changtarget/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Frank Changtarget/riscv: fix rsub gvec tcg_assert_listed_vecop...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Bin Menghw/riscv: Modify MROM size to end at 0x10000
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Atish PatraRISC-V: Support 64 bit start address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Atish Patrariscv: Add opensbi firmware dynamic support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Atish PatraRISC-V: Copy the fdt in dram instead of ROM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Atish Patrariscv: Unify Qemu's reset vector code path
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Bin Menghw/riscv: virt: Sort the SoC memmap table entries
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-14 Bin MengMAINTAINERS: Add an entry for OpenSBI firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: configure and turn on vector extension...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector compress instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector register gather instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector slide instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: floating-point scalar move instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer scalar move instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer extract instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector element index instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector iota instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: set-X-first mask bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vmfirst find-first-set mask bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask population count vmpopc
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask-register logical instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector wideing integer reduction instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer reduction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: narrowing floating-point/integer type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: widening floating-point/integer type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point/integer type-convert...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point merge instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point classify instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point compare instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point sign-injection...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point min/max instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point square-root instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point fused...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point fused...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point multiply
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point add/subtract...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point add...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector narrowing fixed-point clip instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width scaling shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening saturating scaled multiply-add
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width fractional multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width averaging add and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width saturating add and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer merge and move instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer multiply-add...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer multiply instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer divide instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer multiply...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer min/max instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer comparison instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector narrowing integer right shift...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width bit shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector bitwise logical instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer add-with-carry / subtract...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer add and subtract
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer add and subtract
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector amo operations
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add fault-only-first unit stride load
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector index load and store instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector stride load and store instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add an internals.h header
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector configure instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: support vector extension csr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: implementation-defined constant parameters
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 LIU Zhiweitarget/riscv: add vector extension field in CPURISCVState
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-07-02 Alistair Francishw/riscv: Allow 64 bit access to SiFive CLINT
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
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2020-07-02 Jessica Clarkeriscv: plic: Add a couple of mising sifive_plic_update...
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2020-07-02 Jessica Clarkeriscv: plic: Honour source priorities
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2020-06-19 Bin Menghw/riscv: sifive_u: Add a dummy DDR memory controller...
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2020-06-19 Bin Menghw/riscv: sifive_u: Sort the SoC memmap table entries
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU