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tcg/cpu-exec: precise single-stepping after an interrupt
2020-07-14
Ali
s
tair Fran
c
is
hw
/
char: Conve
r
t the Ibex UART to use
the registerfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair
F
rancis
hw/char:
C
onvert
t
he Ibex UART to use the
qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Fra
n
cis
hw
/
riscv
:
Allow 64 bit access to SiFive
C
LINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair Fr
a
n
ci
s
target/ri
s
cv: Use a
smaller guess size f
o
r no-MMU P
M
P
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
st
a
ir Fra
n
cis
r
i
scv/openti
t
an: Connect the UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
r
a
ncis
riscv/opentitan: Con
n
ect the PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/intc: Initial commit of lowRISC
Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/char: Initial commit of
I
bex U
A
RT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r
Fran
c
is
ri
s
cv/ope
n
titan
:
F
ix the ROM
s
ize
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
targ
e
t/riscv: Implement checks
f
or hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
s
t
a
ir Fra
n
cis
tar
g
et/
r
isc
v
:
Move t
h
e
h
f
ence instruct
i
ons
to the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
rancis
target/riscv:
R
e
port
err
o
rs validating 2nd-stage PT
E
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
t
a
rge
t
/
r
i
scv
:
Set access as
data
_
load when validatin
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
sifive
_
e: Support the revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fran
c
is
riscv: I
n
iti
a
l c
o
mm
i
t of OpenTitan machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair
Francis
target/r
i
s
c
v
: Add
the
l
owRISC Ibex
C
PU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
target/riscv: Do
n
't se
t
PMP feature in the cpu init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair Fr
a
ncis
target
/
riscv: Disable the MM
U
corre
c
tly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
target/riscv: D
o
n't
overwrite the rese
t
vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
F
ran
c
i
s
ri
s
cv/boot
:
Add a
mi
s
sing
h
eader include
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Franc
i
s
riscv: sifive_e
:
Manually
d
e
f
i
ne th
e
machi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir
F
r
ancis
docs:
depreca
t
ed
:
Upd
a
te th
e
-bios documentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
ta
i
r Francis
target/riscv: Dr
o
p s
u
pport for
ISA spec ve
r
s
ion 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir Franc
i
s
target/riscv: Remov
e
the depre
c
ated CPU
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
tair
F
rancis
hw/riscv: spike: Remove
d
e
p
recated ISA s
p
e
cific mach
i
nes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv: AND stage-1 and stage
-
2
prote
c
t
i
on flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
risc
v
: Don
'
t use
stage-
2
PTE
l
o
okup prot
e
ction flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Franci
s
r
i
s
c
v
/sifive_u
:
A
dd
a serial
p
roperty to
t
he
s
i
f
iv
e
_u
S
oC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair
F
r
a
ncis
risc
v
/sifive_u
:
Fix up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alistair
Francis
linux-user
:
Support
futex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alist
a
ir Fr
a
ncis
li
n
ux-us
e
r/riscv: Update
t
h
e sy
s
call_nr's to
t
he 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alis
t
air Fran
c
is
linux-user
/
syscal
l
: Add support
for cl
o
ck_gettime64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alist
a
ir Fr
a
ncis
linux
-
user: Protect more syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alistair Francis
targe
t
/riscv: Correctly implement TSR tra
p
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
ancis
tar
g
et/ris
c
v: A
l
lo
w
enabling the Hypervisor exten
s
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
is
target/
r
i
scv: Add the MSTATUS_MPV_ISSET helper mac
r
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
Fran
c
is
tar
g
et/riscv: Add suppo
r
t for the 32-bit MS
T
ATUSH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
target/riscv: Set htval and mtv
a
l2 on execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
ta
r
get/r
i
scv: Rais
e
the ne
w
e
xecptions when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
i
s
ta
r
get/ri
s
cv: Implemen
t
second stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
stair F
r
ancis
target/
r
isc
v
: Allow specifying MMU st
a
g
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Respect MPRV and
S
PRV
f
or floating poin
t
o
ps
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air Francis
t
arge
t
/r
i
s
c
v
: Mar
k
b
o
t
h sstatus and msstatus_h
s
as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
target/ris
c
v:
D
i
s
able g
u
est FP support based on virtual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
tar
g
et/riscv: Only
s
et TB fla
g
s with FP sta
t
u
s
if en
a
bled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
lista
i
r Francis
target/riscv: Remove t
h
e hret instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
target/ri
s
cv: Add hf
e
nce instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Add Hypervisor t
r
a
p
r
eturn suppor
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Francis
t
a
rget/risc
v
: Add hypve
r
visor trap
s
upp
o
rt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
targe
t
/
r
iscv: G
e
nerate
illega
l
inst
r
uction on W
F
I when V=
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
i
s
target/ricsv
:
Flush
t
h
e TLB o
n
v
i
rtuli
s
ation
mode changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
s
t
ai
r
F
r
ancis
t
a
r
get/ri
s
cv: A
d
d
s
upport for virtual interr
u
pt setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
a
ir Francis
target/riscv: E
x
t
e
nd the S
I
P
CSR to support
v
irtulis
a
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target
/
riscv
:
Ex
t
e
n
d th
e
MIE
CS
R
to
s
u
p
p
o
rt
v
irtulis
a
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
is
targe
t
/
ri
s
c
v: Set
VS bits in mideleg fo
r
Hyp ext
e
n
s
io
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: A
d
d
virt
u
al reg
i
ster swapping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Fr
a
ncis
target/riscv:
A
d
d Hypervisor machin
e
CSRs acce
s
ses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
cis
target/ri
s
cv: Add Hyper
v
isor virtual CSRs a
c
c
e
s
s
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/ris
c
v
:
Add Hypervisor CSR access fun
c
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
target/riscv
:
Dump Hy
p
erviso
r
regis
t
ers if ena
b
led
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
target/
r
is
c
v: P
r
int priv a
n
d
v
irt in d
i
sas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair F
r
ancis
t
a
rget/riscv: Fix
C
S
R
perm checking for HS m
o
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
Fra
n
c
is
t
arget/riscv: Add the force HS
e
xcep
t
ion mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air Fr
a
nc
i
s
t
a
rget/riscv: Add the vi
r
tulisatio
n
mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Francis
target/
r
iscv: R
e
n
a
me the H i
r
qs to VS
irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targe
t
/riscv: Add support for the n
e
w execption
n
u
m
bers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
ist
a
ir Francis
targe
t
/riscv: Add th
e
Hyperv
i
so
r
CSRs to CPUSt
a
te
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
t
a
rget
/
riscv: Add the Hypervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir F
r
anci
s
t
a
r
get/riscv: Convert MIP CSR to target_ulong
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
Alistair
F
r
ancis
hw/ar
m
:
Add the Netdu
i
no Pl
u
s 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
A
listair Francis
hw/arm: Add the STM3
2
F
4
x
x
So
C
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
h
w
/
m
isc: A
d
d
t
he STM32F4xx EX
T
I device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
A
listair Franci
s
hw/misc: Add
the
STM32F4xx Sysconfi
g
device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Francis
r
iscv/vir
t
: I
n
c
re
a
s
e
flash size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Franc
i
s
opensbi: Upgrade from v0
.
4 to v
0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
listair Francis
target/r
i
s
cv:
Remo
v
e
atomic
a
ccesses to
MI
P
CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alis
t
air Francis
riscv/boot: Fix possible memory
leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
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2019-10-28
Al
i
stair Fr
a
n
c
is
ris
c
v
/
vi
r
t:
J
ump
to p
f
l
a
sh i
f
speci
f
ied
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
Alistair Francis
riscv/v
i
rt: Add the PF
l
ash
C
FI01 devic
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
A
l
i
s
tair
Francis
riscv/virt:
Ma
n
ually define
the mac
h
ine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
A
listair Franc
i
s
r
i
scv/sifive_u: Ad
d
the start-in-flash property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
Alistair Francis
riscv/s
i
f
ive_u
:
M
anually
d
efi
n
e
t
he machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
Alistair Fran
c
is
ris
c
v
/sifi
v
e_
u
: Add QSPI memory region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
Alistair Francis
riscv/sifive_
u
: Add
L
2
-LIM cache
memor
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alistair Francis
target/risc
v
: U
s
e TB_F
L
A
G
S_MSTATUS_FS for floati
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Al
i
stair Fra
n
cis
t
a
r
get/riscv: Fix m
s
tatus d
i
rty mask
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Ali
s
tai
r
Francis
t
a
rget/riscv: Update the
H
ypervisor CSRs to
v
0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
A
listair Francis
t
ar
g
e
t
/
ri
s
cv: Create fu
n
c
t
ion to test if FP is enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
Alistair Franc
i
s
ri
s
cv
:
plic: Remove
unused
inte
r
rupt fun
c
tion
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-26
A
l
istair Franci
s
riscv/boo
t
:
Fixup the RI
S
C
-V firmware warning
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-18
A
l
istair Francis
h
w
/riscv: Load OpenSBI as the defa
u
lt fi
r
mw
a
re
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-18
Ali
s
tair F
r
a
ncis
ro
m
s: Add Op
e
n
S
BI version 0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-09
Alista
i
r
Fr
a
n
c
is
tcg/riscv: Fix RISC-VH host build fa
i
lure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
A
l
i
stair Francis
hw/riscv: Extend th
e
kernel loading
su
p
p
or
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
Alista
i
r Francis
hw/r
i
s
c
v
:
A
d
d support for
loadi
n
g a firmw
a
re
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-27
Alist
a
i
r
F
r
ancis
hw/ris
c
v: Sp
l
it out the boot functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Al
i
stair Francis
t
a
rget
/
riscv:
A
dd support for disab
l
ing/enabling Co
u
n
t
ers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alista
i
r F
r
ancis
targe
t
/ris
c
v
: R
e
move us
e
r versi
o
n information
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alistai
r
Francis
t
a
r
g
e
t/ri
s
cv: Require ei
t
he
r
I o
r
E
ba
s
e
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-06-25
Alistair Fran
c
i
s
q
emu-deprecated
.
texi: Deprecate the R
I
SC-V
p
riv
l
edge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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