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riscv: sifive: Implement a model for SiFive FU540 OTP
2019-09-17
B
in Meng
r
i
s
cv:
sif
i
ve:
Implement a mo
d
el for SiFive FU5
4
0 OTP
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: roms: Update d
e
fau
l
t bios for s
i
five_u machine
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: sifive_u: Cha
n
ge
UART node
name in d
e
vice tree
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Update UART ba
s
e addr
e
sses
and
I
RQs
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v:
s
ifiv
e
_u: Reference PR
C
I
clo
c
ks
i
n UART and
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
sifi
v
e_u: Add PRCI bloc
k
to th
e
SoC
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifive_u:
Ge
n
erate hfclk and rtcclk nodes
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive: Im
p
l
e
ment PRCI
m
odel for
F
U540
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v:
sifive_u: Updat
e
PLIC hart
t
opolog
y
configuration
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: s
i
five_u: Up
d
a
t
e ha
r
t configurat
i
on to reflec
t
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
c
v
: sifive_
u
:
S
et the minimum number of
cpus t
o
2
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
ris
c
v: hart: Add
a
"
h
a
r
t
id
-
ba
s
e" property to RISC-V
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
eng
ris
c
v: ha
r
t
:
Ex
t
ract
h
a
rt r
e
alize to a separate
r
o
utine
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
ng
riscv: Add a
sif
i
v
e
_
cpu
.
h to include bot
h
E and U cpu
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
M
eng
r
i
scv: sifi
v
e_
e
:
Dr
o
p sifive
_
mmio_emulate()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifiv
e
_e: pr
c
i:
U
pdat
e
the PRCI register block
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
s
i
five_e: pr
c
i: Fix a t
y
po of
hfx
o
scc
f
g
r
egis
t
er
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
ri
s
cv: sifive: Rename sifive_
p
rci
.
{c, h} t
o
sifive_e_prci
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv:
s
i
f
ive_u: Remove th
e
u
nnecessary in
c
lude of
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: roms: Remove
e
x
ecuta
b
le attribute o
f
opensbi
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: hw:
Remove the unne
c
essa
r
y include
o
f tar
g
et
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Meng
riscv: h
w
:
Change to use qemu
_
log_
m
ask(LOG_GUEST_ERROR
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
:
hw: Change create_fdt() to
r
e
t
ur
n
voi
d
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: hw:
Rem
o
ve
n
ot needed PLIC pr
o
p
e
rties in de
v
ice
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
r
i
scv: hw:
Use qemu_fdt_
s
e
t
prop_cell()
f
or property
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: hw
:
Remove sup
e
rfluous "linux, phandle
"
proper
t
y
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
s
c
v
: hw: Remove duplicat
e
d "hw/
h
w
.
h" inclu
s
i
o
n
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
M
e
ng
riscv: sifive_test: Add
r
e
s
e
t
fu
n
ctionali
t
y
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
r
i
scv: hm
p
: Add
a
comma
n
d to show virtual
m
emory map
p
ings
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: Resolve
full path of the given bios image
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: Add a
helper routi
n
e f
o
r fin
d
ing firmwar
e
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv
:
r
v
32: Root pag
e
t
abl
e
a
d
d
ress can be
lar
g
er
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Al
i
s
t
air Francis
t
a
r
get/ris
c
v
:
Update the
Hyperv
i
s
o
r C
S
R
s
to v
0
.
4
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
A
l
istair Francis
target/
r
i
scv: Create function
to test if F
P
is enabled
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Franci
s
riscv:
p
lic: Remove unused int
e
rrupt functio
n
s
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
P
hilip
p
e Mathieu
.
.
.
tar
g
et/riscv/p
m
p
:
Co
n
ve
r
t qemu
_
lo
g
_mask(LOG_TRACE)
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Philippe Mathieu
.
.
.
target/riscv/p
m
p
:
Re
s
t
rict p
r
iviledged PMP to sys
t
em
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Guenter Roeck
riscv: sifive_u: Fi
x
clock-n
a
mes pro
p
erty for ethernet
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
G
u
e
nter Roeck
riscv: sivive_u: Add dummy serial clock and ali
a
ses
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Guenter Roeck
ris
c
v:
s
ifi
v
e_u: A
d
d support for loading
i
n
i
t
rd
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-26
Al
i
st
a
ir Francis
riscv/boot:
F
ixup the R
I
SC-V firmware warning
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-18
Al
i
stair Francis
hw/riscv: Loa
d
Ope
n
SBI a
s
the default firmwa
r
e
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-18
A
listair
Fr
a
ncis
roms
:
Add OpenSBI
version 0
.
4
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Alis
t
air Fran
c
is
hw/ris
c
v
:
Ex
t
e
n
d the ke
r
nel lo
a
d
i
ng support
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Al
i
stair Francis
hw/riscv:
Ad
d
sup
p
ort for loadin
g
a
fi
r
mware
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Alis
t
air
Fran
c
is
hw/riscv: Split out the boot fun
c
tion
s
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Bin Me
n
g
riscv: sif
i
v
e
_u: Update t
h
e
plic hart co
n
fig to support
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Bin Meng
r
i
s
c
v: sifive_u: Do not create har
d
-c
o
ded phandles
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Wlad
i
mir J
.
va
n
.
.
.
disas
/
riscv
:
Fix `rdin
s
treth`
c
onstraint
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Mic
h
ael
C
lark
disas/riscv: D
i
sassemble rese
r
ved compress
e
d
en
c
odings
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Ati
s
h Patr
a
r
i
scv: v
i
rt: Add cpu
-
topolo
g
y DT
n
o
d
e
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Jim Wilson
RISC-V: Update
s
ys
c
all l
i
st for 32-bit
s
upp
o
rt
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
J
oel
Si
n
g
RISC-V: Clear load reservations
o
n context swit
c
h a
n
d SC
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Palm
e
r Dabbelt
RIS
C
-
V
:
Add su
p
port for
t
h
e
Zicsr ex
t
ensi
o
n
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Palmer Dabbelt
R
ISC
-
V: A
d
d supp
o
rt for the
Zifencei extens
i
on
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
target/risc
v
: Add support for disabli
n
g
/enablin
g
Coun
t
ers
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alistai
r
Francis
target/riscv: Remove
u
s
er v
e
rsio
n
information
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alist
a
ir Francis
target/r
i
s
c
v: Req
u
ire either I or E base extension
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alist
a
ir Fra
n
cis
qe
m
u-deprecated
.
texi: Deprecate
t
he RISC-V
privledge
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alistair
F
rancis
ta
r
get/r
i
scv: Set pr
i
vl
e
dge spec 1
.
11
.
0 as default
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alista
i
r Francis
t
a
rget/riscv: Add
the
mcountinhibi
t
CSR
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Alistair Fr
a
nc
i
s
t
a
rget/
r
is
c
v:
Add th
e
p
rivledge spec version 1
.
11
.
0
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Alistai
r
Franci
s
t
a
rg
e
t/riscv:
R
estructu
r
e de
p
recatd CPUs
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Palm
e
r Dabbelt
R
ISC-V: Fix a memo
r
y leak w
h
en realizing a sifiv
e
_e
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Bin Meng
ri
s
cv:
virt: Corr
e
ct pci
"bu
s
-
ran
g
e" enc
o
ding
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hesha
m
Almatary
RIS
C
-V: Fix a PMP chec
k
with the correct access s
i
ze
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hesham Almatary
RISC-V: Fi
x
a PMP bug
where it succeeds eve
n
i
f PMP
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hes
h
am Almatary
RISC-V: Check PMP
duri
n
g
Page Table Walks
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hesham Alm
a
tary
R
IS
C
-V:
Check
for the effectiv
e
memor
y
p
rivilege
mode
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
H
esham Almatar
y
RISC-V: Rai
s
e acces
s
fau
l
t
ex
c
epti
o
ns on PMP v
i
olations
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
H
e
s
h
am Almatary
R
ISC-V: Only Check PMP if MMU translati
o
n succeed
s
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Mi
c
hael Clark
t
arget/riscv: I
m
plement ri
s
cv_cpu_unassigned_access
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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2019-06-24
Dayeo
l
L
ee
target/ri
s
cv:
Fix
PMP range
boundary
address
b
u
g
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-06-24
N
a
thaniel Graff
sifiv
e
_
p
rci: Read and write
PRCI
r
eg
i
sters
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-06-24
Alistair Francis
t
arget/riscv: Allow setting I
S
A extensions via CPU
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Jonath
a
n Beh
r
e
ns
target/r
i
s
c
v: On
l
y
f
lush TL
B
if
S
ATP
.
ASID changes
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Jonathan Behrens
target/r
i
scv: More accur
a
te
h
a
n
dling of `sip`
CSR
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Richard Henderson
target/riscv: Add
checks for several RVC res
e
r
v
e
d
operands
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Alistair
F
ran
c
is
target/ris
c
v
:
Add the HG
A
TP reg
i
ster masks
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alis
t
air Francis
t
a
rget/ri
s
cv: Add the HSTATUS registe
r
masks
Reviwed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
A
l
istair Franci
s
targ
e
t/riscv: Add Hypervisor
C
S
R macros
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alistair Francis
target/riscv:
A
l
low setting mstatus virt
u
lisation bits
Revieweb-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Alistair Francis
target/
r
iscv: Add
the MPV and MTL mstatus
bits
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
A
l
istair
F
ranc
i
s
target/r
i
scv: Impro
v
e
t
h
e
scause logic
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Alistair
Fr
a
ncis
t
a
rget/riscv: Trigger int
e
rr
u
pt on MIP up
d
ate asynchro
n
ous
l
y
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Alist
a
ir Francis
target/riscv: Mark privilege l
e
vel 2 as res
e
r
ved
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Al
i
sta
i
r Francis
risc
v
: spike
:
Add a generic s
p
ike mach
i
ne
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alistair
F
rancis
tar
g
et/riscv: Deprecate the ge
n
e
ric no
MMU C
P
Us
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alista
i
r
Francis
target/riscv: Add a base 32 and 64 bit CP
U
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alistair Francis
t
arget/riscv
:
Create settable CPU
prope
r
ties
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
Alistair
F
r
ancis
ri
s
cv: vi
r
t
:
All
o
w specif
y
i
ng a CPU v
i
a co
m
mandline
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Alistair Franci
s
li
n
ux-user/riscv: Add the CPU
t
ype as a co
m
m
ent
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Jonathan Behr
e
n
s
target/riscv:
Re
m
ove unused include o
f
riscv_h
t
if
.
h
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Richard Henderson
t
a
rget/riscv: Re
m
ove
s
p
ac
e
s fr
o
m regi
s
ter
names
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Richa
r
d H
e
nderson
target/riscv: Sp
l
it gen_arith_i
m
m into functional
a
nd
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Rich
a
r
d
Hender
s
on
target/riscv
:
S
p
lit RVC
3
2 and
RVC64
i
n
sns into separate
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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tree
2019-05-24
R
ic
h
ar
d
H
enderson
tar
g
e
t
/riscv
:
Use pattern groups in
insn16
.
decode
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
Ri
c
hard He
n
derson
target/riscv: M
e
rge argum
e
n
t
dec
o
de f
o
r RVC shifti
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
R
i
c
hard Hend
e
rson
t
a
rge
t
/riscv: Merge arg
u
ment sets
f
o
r
in
s
n32 and i
n
sn16
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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commitdiff
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tree
2019-05-24
R
ich
a
rd
Henderson
targ
e
t/riscv:
U
se
--sta
t
i
c-decode
for dec
o
de
t
ree
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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