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target/riscv: Convert MSTATUS MTL to GVA
2020-08-25
Alistair Fran
c
is
ta
r
get/riscv
:
Convert MSTATUS
M
TL to GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
a
ir
Francis
target/riscv: Don'
t
a
l
low
gu
e
st to w
r
i
t
e to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istai
r
Franc
i
s
tar
g
e
t
/riscv: Do
two-s
t
age loo
k
ups on
hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stair
F
rancis
t
a
rget/risc
v
: Allow
generating hlv/hlvx/hsv
instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
list
a
ir Francis
target/riscv: Allow sett
i
ng a two-stag
e
l
o
o
kup
i
n the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Fran
c
is
hw/intc: ibex_plic: Ho
n
our
source priorities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Fran
c
is
hw/intc: ibex_plic: Don't allo
w
repeat interrupts
on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alist
a
i
r
F
r
a
ncis
hw/intc: ibex_plic: Update the pending irq
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alistair F
r
ancis
h
w/sd/p
l
181: Rep
l
a
c
e
fprintf(
s
t
d
err,
"
*\n") with error
_
repo
r
t()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
A
listair Francis
hw/char: Convert
th
e
Ibex UA
R
T to use the regi
s
terfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
A
l
istai
r
F
rancis
h
w/char: Convert th
e
Ibex
U
ART t
o
u
s
e the qdev Clo
c
k
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Ali
s
tair
F
r
a
n
c
is
hw/riscv: Allow 64 bit acces
s
t
o
SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
target/risc
v
: Use a smaller guess
s
i
z
e for
n
o-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alis
t
a
ir
F
rancis
ri
s
cv/openti
t
a
n:
C
onnec
t
the UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Fran
c
is
r
i
scv
/
opentitan:
C
onnect the PLI
C
d
e
vice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
Francis
hw/intc: Initial comm
i
t o
f
lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
t
a
i
r Francis
hw/char: Initial c
o
mmit of Ibex
UAR
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
Francis
riscv/o
p
entitan
:
Fix
t
he RO
M
size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
i
stair Fran
c
is
ta
r
get/riscv:
I
mplement checks for hf
e
nce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
is
t
air Fran
c
i
s
targ
e
t/ri
s
cv: Move
the hfence instr
u
c
tions
to
the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Franc
i
s
t
a
r
get/riscv: Report errors
v
al
i
dat
i
ng 2nd-stage PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair Franc
i
s
target/
r
iscv
:
S
e
t access
a
s dat
a
_load when val
i
dating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Francis
s
i
f
ive_e: Support the rev
B
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Fra
n
c
i
s
riscv: Init
i
a
l
c
o
mmit of OpenT
i
t
an mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alis
t
air
F
rancis
ta
r
g
e
t/riscv
:
Add the lowRISC Ibex C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Fran
c
is
target/riscv:
Don't s
e
t PMP feature in the cpu in
i
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franci
s
t
ar
g
et/riscv:
D
isable the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
target
/
riscv: D
o
n't ove
r
write t
h
e
rese
t
v
e
ctor
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv/
b
oot: Add a
mi
s
sing
h
eader in
c
lude
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
ancis
riscv:
s
ifi
v
e_e: Man
u
ally
d
efine the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Fran
c
is
doc
s
:
deprecated: Update the
-
bios documentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
s
tair Fra
n
cis
t
a
r
g
e
t/ris
c
v: D
r
op supp
o
rt
f
or I
S
A spe
c
version 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Fra
n
cis
target/riscv: Remove the dep
r
ecate
d
CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
hw
/
r
i
scv: s
p
ike: Remove d
e
precated ISA specific machine
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Fr
a
ncis
ri
s
cv
:
AND stage-1 and stag
e
-2 pr
o
tectio
n
f
l
ags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair
Fra
n
cis
riscv: Don't use sta
g
e-2 P
T
E
l
ookup prote
c
tion flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Ali
s
tair Franc
i
s
risc
v
/sif
i
ve_u: Add a se
r
ial property to
the si
f
iv
e
_
u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Al
i
stair Francis
riscv/
s
ifive_u: Fix u
p
fil
e
orde
r
ing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alistai
r
Francis
linux-user: Support fut
e
x_
t
ime64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
li
n
ux-u
s
er/riscv: Upd
a
te the syscall_n
r
's to th
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
linux-us
e
r
/
sys
c
a
l
l: Add support for cloc
k
_gettime64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair
F
ran
c
i
s
l
inux-user: Pro
t
e
c
t mo
r
e syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alistair Francis
targ
e
t/ri
s
cv:
C
orrectl
y
implement TS
R
t
r
ap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Francis
tar
g
et/riscv: Allow enabling the Hyper
v
isor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
tar
g
et/riscv: Add the MSTATU
S
_MPV_I
S
SET helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Francis
t
a
rg
e
t/risc
v
: Add su
p
port for the 32-bit MST
A
TUSH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
target/riscv:
Set htval
and m
t
val2
on execp
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Fr
a
ncis
target/ris
c
v: Ra
i
se the new e
x
e
cptions wh
e
n 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Fra
n
cis
target
/
ri
s
cv: Implement se
c
ond stag
e
M
M
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
t
a
rg
e
t/riscv: Allow specifying MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
a
n
cis
tar
g
e
t
/riscv: Respect MPRV an
d
SPRV fo
r
floati
n
g point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
t
a
r
get
/
riscv: Mark
b
oth sstatus
and ms
s
t
atu
s
_h
s
as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair Francis
t
a
rget/riscv: Di
s
able
gu
e
st F
P
sup
p
o
rt base
d
o
n
virtual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
li
s
tair Francis
tar
g
et/riscv: Only s
e
t
TB flags
w
ith FP status if e
n
a
b
l
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair F
r
anc
i
s
targe
t
/riscv: Remove the
hret
i
ns
t
ruct
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
ta
r
ge
t
/riscv: Add
h
fence instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
cis
target/risc
v
:
Ad
d
Hypervisor trap ret
u
rn s
u
pport
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
ta
r
ge
t
/r
i
scv:
Add hypvervisor
trap s
u
pport
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
cis
t
arget/riscv: Generat
e
il
l
egal ins
t
r
uction o
n
WFI whe
n
V
=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
i
r Fran
c
i
s
t
arget/ricsv:
Flush the TL
B
on
v
irtuli
s
a
t
ion mode
chan
g
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
i
s
target/riscv: Add suppo
r
t for virtual interrupt set
t
ing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir F
r
ancis
target/riscv:
E
xtend the SIP CSR to support virtuli
s
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
r
ancis
target/risc
v
: Extend the MIE CSR
t
o support virtulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
ancis
targ
e
t
/r
i
scv: Set VS bits in mideleg f
o
r
Hyp extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
ta
r
get/r
i
sc
v
: Add virtual register swappi
n
g fun
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Francis
tar
g
et
/
riscv: Add Hypervisor machine CSRs acc
e
sses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
F
rancis
target/riscv
:
Add Hypervisor virtu
a
l C
S
Rs ac
c
esses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Francis
target/riscv: Ad
d
Hypervi
s
o
r
CSR acces
s
fu
n
ct
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Fran
c
is
tar
g
e
t/riscv:
D
ump
Hypervisor register
s
i
f enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Franci
s
tar
g
et/risc
v
: Print priv and virt in disas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair Francis
t
a
rget/ri
s
cv
:
F
i
x CSR perm checking
for HS mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir Francis
targ
e
t
/
riscv: A
d
d t
h
e force HS exception mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair F
r
anc
i
s
target/ri
s
c
v: A
d
d t
h
e virtu
l
i
sati
o
n
mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
cis
t
a
rget/riscv: Rename the H
i
r
q
s to
V
S i
r
qs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
l
i
s
tair Fran
c
is
targ
e
t/riscv: Add support for the new execption numbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fra
n
ci
s
target/riscv:
Add
t
he
H
ypervisor C
S
Rs to CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
s
tair Fra
n
c
is
tar
g
et/riscv:
A
d
d the Hy
p
erv
i
s
o
r
e
x
t
e
nsion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
tair
F
rancis
targe
t
/riscv: C
o
nvert
M
IP CS
R
to tar
g
et_ulong
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-01-17
Alistair F
r
anci
s
h
w/arm: Add the Netduino Plus 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
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2020-01-17
A
listair
F
ran
c
i
s
h
w
/arm: Ad
d
the
S
TM32F4xx SoC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
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2020-01-17
Alistair Francis
hw/misc: Ad
d
the STM32F4
x
x EXT
I
dev
i
ce
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
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2020-01-17
Alis
t
ai
r
Francis
hw/m
i
sc: Add the STM32F4
x
x
Sysc
o
nfig de
v
ice
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
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2019-11-14
Alistair Francis
r
iscv/vir
t
: Increase
flash s
i
ze
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-11-14
Alistair
Francis
ope
n
sbi:
Upgra
d
e from v0
.
4 to v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-11-14
Alistair Francis
t
a
r
get/riscv: Remove atom
i
c
a
c
c
esse
s
to MIP CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
A
l
ista
i
r
Fr
a
ncis
r
iscv/
b
o
ot: Fix possible
m
e
mory leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2019-10-28
Alis
t
air Francis
riscv/virt:
J
ump to
p
f
l
a
s
h if spec
i
fied
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
Alistair
Francis
ri
s
cv/
v
irt: Add
the P
F
lash CF
I
01 devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2019-10-28
Alistair
F
rancis
riscv/v
i
rt: Manually
d
efine
the machin
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2019-10-28
A
listair Francis
riscv/sif
i
ve
_
u: Add the start-i
n
-flash p
r
ope
r
t
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-10-28
Alistair Francis
riscv/sifive_u: Man
u
al
l
y
d
e
fine the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2019-10-28
Alistair Francis
riscv/sifive_u:
A
dd QSPI memory region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-10-28
A
l
istair Francis
riscv/sifive_u: Add L2-L
I
M cache memory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-09-17
Alistair Franc
i
s
target/ri
s
c
v: Use TB_FL
A
GS_
M
STATUS_FS
for floating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-09-17
A
l
i
stai
r
Franci
s
target/riscv: Fix ms
t
atus dirty
m
ask
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-09-17
Alis
t
air
F
rancis
tar
g
et/riscv:
U
pdat
e
th
e
Hype
r
visor
C
SRs to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-09-17
Alistair Francis
target/riscv: Create function to test
if FP
is enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-09-17
Alistair Fran
c
is
riscv: plic:
R
emove u
n
used i
n
terrupt f
u
nc
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-07-26
A
listair Franc
i
s
riscv/boot:
F
ixup the RISC
-
V f
i
rmware warning
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2019-07-18
Alistair
F
rancis
h
w
/
riscv: Load OpenS
B
I as
th
e
defa
u
l
t f
i
rmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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