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target/riscv: vector integer comparison instructions
2020-07-02
Al
i
stair Francis
hw/riscv: Allow 64
bi
t
acc
e
ss to
SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
ancis
targe
t
/
r
iscv: Use a smaller guess
s
i
ze for n
o
-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
ri
s
cv/opentitan:
C
o
n
n
ect th
e
UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franci
s
riscv/o
p
en
t
itan: C
o
nnect
t
he PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/intc:
I
ni
t
i
a
l c
o
mmit of lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw
/
char
:
Ini
t
ial commit of Ibex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
r
isc
v
/open
t
itan: Fix the ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair Fra
n
cis
target/ri
s
cv: Implement checks for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Francis
target/ri
s
cv: Mov
e
t
h
e hfence instructions to the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
ta
r
get/riscv: Re
p
ort errors va
l
idat
i
ng 2nd-
s
tage PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Francis
target/riscv: Set a
c
cess as d
a
ta_load w
h
en
validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
s
i
five_e: Support t
h
e revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
a
n
c
is
r
i
scv: In
i
t
i
al commit of
O
penTitan mac
h
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
tair Francis
targe
t
/riscv: Add the
lowRISC Ibex C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair Franc
i
s
target/riscv: Don't s
e
t
PMP feature in the cpu
i
nit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir Francis
target/riscv:
D
isable the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
listai
r
Fr
a
ncis
target/r
i
scv: Don't overwrite the
re
s
et vect
o
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistai
r
Fran
c
is
ris
c
v/bo
o
t: Add
a missing header incl
u
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fran
c
is
riscv: sifive_
e
:
Manual
l
y define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
s
t
air Francis
docs:
d
eprecated:
Up
d
ate th
e
-bios docu
m
e
ntation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
tair Fr
a
ncis
ta
r
g
e
t/riscv: Dro
p
suppo
r
t
f
or ISA sp
e
c
v
ersion 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fra
n
ci
s
tar
g
e
t
/ri
s
cv: Remove the deprecated CP
U
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
h
w
/riscv: spike:
R
emove deprecated
ISA s
p
e
cific machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair
F
rancis
r
i
scv:
AND stage-1 and stage-2 protect
i
on
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv: Don't u
s
e stage
-
2 PTE lookup protection
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Ali
s
tair Francis
ris
c
v/sifive_u: Add a serial property to the sifive_u
S
oC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair
Fr
a
n
cis
r
iscv/sifive_u: F
i
x up file o
r
der
i
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alistair Franc
i
s
l
i
nux-user: Sup
p
ort futex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair
F
r
ancis
l
i
nux-use
r
/riscv: Update t
h
e syscall_nr's to
t
h
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair F
r
ancis
linu
x
-user
/
s
yscall: Add support
f
or
c
lock_g
e
ttime64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alistair Francis
li
n
ux-user: Protect more syscal
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alistair Francis
target/riscv: Cor
r
ec
t
ly imple
m
ent
TSR trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair F
r
ancis
ta
r
get/riscv:
A
ll
o
w
e
nab
l
i
n
g the
Hypervisor exte
n
sion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir F
r
an
c
is
t
a
rget/ri
s
cv: Add the MSTATUS_MPV_ISSET he
l
per macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franci
s
target/riscv: Ad
d
support for the 32-bit MSTATUSH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target
/
r
i
scv: Set htv
a
l and m
t
v
al2 o
n
execptio
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Franci
s
target/riscv: Ra
i
s
e
the new execpt
i
ons when 2nd
s
t
age
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair F
r
ancis
t
a
rget/riscv
:
Implement second stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stai
r
Franci
s
target/riscv:
A
l
l
ow specifying MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listair F
r
ancis
ta
r
g
et/riscv
:
Respect MPRV and SPRV for float
i
ng point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair
F
ranci
s
target/riscv: Mark bo
t
h sstatus
a
nd msstatus_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Franc
i
s
target/riscv: Disable guest FP supp
o
rt
based o
n
vir
t
ual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair
Franc
i
s
target/riscv: Only se
t
TB
f
lags with FP stat
u
s if
e
nabl
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istai
r
Fr
a
n
cis
ta
r
ge
t
/riscv: Remove the hret ins
t
ruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
ranc
i
s
t
arget/riscv: Add hfence instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/r
i
scv: A
d
d Hypervisor
trap
return support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Fra
n
cis
t
arget/riscv:
Add hypver
v
isor tra
p
support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Fran
c
is
t
arget/riscv: Gen
e
rate ill
e
gal instruction
o
n WFI whe
n
V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
t
arget/ricsv: Flush the TLB on virtulisation mode changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Francis
targ
e
t
/
ris
c
v: Add supp
o
rt
f
or virtual
interrup
t
setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
i
s
target/riscv
:
Extend the SIP
CSR to support virtulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Extend the MIE CSR to support v
i
r
t
ulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
li
s
tair Francis
target/risc
v
: Set VS bits in
midele
g
for Hy
p
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air
Francis
target/riscv: Ad
d
virtual
r
egiste
r
swapping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
a
n
cis
t
a
rget/riscv: Add
Hyper
v
i
so
r
mac
h
ine CSRs acces
s
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv:
Add Hyp
e
rvisor vir
t
ual CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
rancis
target/
r
is
c
v:
A
d
d
Hypervisor CSR access
functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
t
a
ir Francis
target/ris
c
v
:
D
u
mp Hy
p
e
r
viso
r
regis
t
ers if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
stair
Fran
c
is
targe
t
/r
i
scv: Print
p
riv
and
v
i
rt
in d
i
sas
l
og
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Fix CSR perm checking for HS mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Fra
n
cis
t
a
rget/ri
s
cv
:
Add the forc
e
HS excep
t
io
n
mo
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv
:
Add th
e
v
i
rtulisation mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
a
n
c
i
s
targ
e
t/riscv: Rename the
H
irqs to V
S
irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
Fran
c
is
target/riscv: Add support for the
new exec
p
tion
n
umbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
cis
target/r
i
scv: Add t
h
e
Hypervisor CSRs to CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target
/
riscv: Add
t
he Hypervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franci
s
target/riscv: C
o
n
v
ert MIP
C
SR to
t
arge
t
_u
l
o
n
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
Al
i
st
a
ir Francis
h
w/arm: Add
the
N
etd
u
i
no Plus 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
A
l
ista
i
r Francis
hw/arm: Add the STM32F4xx SoC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw/m
i
sc: Add the STM32F4xx EXTI device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alista
i
r Francis
hw/misc: Add the S
T
M32F
4
xx Sysconfig
d
e
vic
e
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Franc
i
s
riscv/v
i
rt:
I
nc
r
ease flash si
z
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
Ali
s
tair Francis
op
e
nsb
i
: Upgr
a
d
e from v0
.
4 to v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
l
istair Francis
t
a
rget/riscv: Remove atomic accesses to MIP CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair
F
rancis
riscv/boot: F
i
x po
s
sible mem
o
ry
l
e
a
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair F
r
anci
s
riscv/virt: Jump
t
o
pflash if speci
f
i
ed
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
stair Francis
riscv/virt: Add
the P
F
lash
C
F
I
01
device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
t
a
i
r
Fr
a
ncis
riscv/virt:
M
anual
l
y define th
e
mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
lis
t
air
F
r
anci
s
ris
c
v/sifive
_
u: Add the
s
t
a
rt-in-fla
s
h property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-10-28
Al
i
stair Francis
riscv/sifiv
e
_u: Manuall
y
define the
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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commitdiff
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tree
2019-10-28
Al
i
stair Franci
s
risc
v
/sifive_u: Add QSP
I
m
emory
regio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-10-28
Alistair Fr
a
ncis
riscv/sifive_u: Ad
d
L2-LIM cache memory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-09-17
A
l
i
s
t
a
ir Francis
ta
r
get/riscv
:
Use TB_FLAGS_
M
STATUS_
F
S
fo
r
f
l
oating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-09-17
Alistair Francis
tar
g
et/riscv
:
Fix
m
status dirty mask
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-09-17
A
l
istair Francis
t
a
rg
e
t/riscv: Update the Hypervisor CSRs to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-09-17
Alistair Franc
i
s
target/riscv: Crea
t
e func
t
ion
to test if FP is enabl
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-09-17
Alistair F
r
ancis
riscv: plic: Remove unused interrupt
funct
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-07-26
Alistair
Fra
n
c
i
s
r
i
s
cv/b
o
ot: Fixup t
h
e RI
S
C-V
firmware
warn
i
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-07-18
Alistair Fr
a
ncis
h
w
/riscv: Loa
d
OpenSBI as the default firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-07-18
Alistair Francis
rom
s
:
Add OpenSBI version 0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-07-09
Ali
s
tair F
r
ancis
tcg/ri
s
c
v: Fix RISC-VH
ho
s
t build failure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-27
A
l
ist
a
ir Fr
a
n
c
i
s
hw/riscv: Exte
n
d the k
e
rnel
l
oading support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-27
Alistair Francis
hw/
r
isc
v
: Add supp
o
rt for loading a fi
r
mware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-27
Ali
s
tai
r
F
ranc
i
s
hw/riscv
:
S
p
lit out the b
o
ot f
u
nc
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-25
A
l
istair
Francis
targ
e
t/ris
c
v: Add
s
upport for
disabling/enabl
i
n
g Cou
n
ters
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-25
Alistair Francis
tar
g
et/riscv
:
Remove use
r
version information
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-25
A
l
ist
a
ir Francis
targe
t
/risc
v
: Re
q
ui
r
e
ei
t
her I or E base extensi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-25
Alistair Francis
qemu-deprecated
.
texi
:
Deprecat
e
the RISC-V privled
g
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-06-25
Alistair Fran
c
is
target/riscv: Set privled
g
e spec
1
.
11
.
0 as default
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2019-06-25
Alistair F
r
anc
i
s
target/riscv: Add th
e
mcountinh
i
bit CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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