repo.or.cz
/
qemu
/
ar7.git
/
search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
first
·
prev
·
next
hw/riscv: spike: Change the default bios to use generic platform image
2020-08-22
Bin Meng
hw
/
riscv
:
spike:
C
h
ange the de
f
ault bios
to use generic
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w/riscv: Use pre-bu
i
lt
b
ios image
o
f
gene
r
ic
p
l
atform
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
ro
m
s/Ma
k
efile: Build the generic
platfor
m
for RISC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
roms/opensbi: Upgrade from v0
.
7
t
o v0
.
8
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
configure: Creat
e
s
y
mbolic links for pc-bios
/
*
.
elf
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/riscv: sifive
_
u
:
Add
a
dummy L2 cache controll
e
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw
/
riscv: Modify MROM
si
z
e to
e
nd at 0x100
0
0
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv
:
virt:
S
ort the SoC m
e
mmap t
a
ble en
t
ries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifi
v
e_u:
A
d
d
a
d
ummy DDR memor
y
controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v: s
i
f
ive_u: Sort the SoC m
e
mma
p
table e
n
tries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u:
S
upport different boot so
u
rce p
e
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifive: Change SiF
i
v
e E/
U
C
PU re
s
et v
e
ct
o
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
target/riscv: Rename IBEX CPU init rou
t
ine
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_
u
:
A
dd a new pr
o
perty msel for MSEL
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
i
f
ive_u: Rename se
r
ial property get
/
s
et
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_u
:
Add res
e
t functionality
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/ris
c
v: si
f
ive_gpi
o
: Do not blindly trigger output
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifiv
e
_u: Hook a GPI
O
con
t
ro
l
l
er
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
h
w
/riscv: s
i
f
ive_gpio: Add a new
'
n
g
pio' pr
o
perty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
h
w/
r
iscv: sifive_gpio: Clean up the codes
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive_u: Genera
t
e device
t
ree node for OTP
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifive_u: Simplif
y
t
he GEM IRQ
conn
e
ct code
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: opentitan
:
Remove the
r
isc
v
_
pr
e
fix of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv: sifiv
e
_e:
Remove the
riscv_ prefix of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
riscv: Keep the
C
PU in
i
t
rout
i
ne na
m
es
consistent
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v:
G
e
neralize
CPU ini
t
ro
u
t
ine fo
r
t
h
e ima
c
u
C
PU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
riscv: Ge
n
eralize C
P
U ini
t
rout
i
ne f
o
r the gcsu CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
riscv: Ge
n
e
ralize CPU i
n
it routi
n
e for the ba
s
e
C
PU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin Men
g
hw/
r
iscv: virt
:
Remov
e
t
he ri
s
c
v
_ pref
i
x of the
machine
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin
M
eng
hw
/
ri
s
cv: sifive
_
u: Remove
t
h
e
r
iscv_
p
refix of
t
h
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
riscv: Chang
e
t
h
e defa
u
lt be
h
av
i
o
r i
f
no -bio
s
op
t
ion
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
r
iscv: Suppress
th
e
error report for QEMU testing with
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
