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2019-11-01	Palmer Dabbelt	MAINTAINERS: Change to my personal email address Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Dayeol Lee	target/riscv: PMP violation due to wrong size parameter Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/boot: Fix possible memory leak Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Jonathan Behrens	target/riscv: Make the priv register writable by GDB Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Jonathan Behrens	target/riscv: Expose "priv" register for GDB for reads Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Jonathan Behrens	target/riscv: Tell gdbstub the correct number of CSRs Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Jump to pflash if specified Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Add the PFlash CFI01 device Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Manually define the machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add the start-in-flash property Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Manually define the machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add QSPI memory region Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add L2-LIM cache memory Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Giuseppe Musacchio	linux-user/riscv: Propagate fault address Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: sifive_u: Add ethernet0 to the aliases node Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: hw: Drop "clock-frequency" property of cpu nodes Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Palmer Dabbelt	RISC-V: Implement cpu_do_transaction_failed Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Palmer Dabbelt	RISC-V: Handle bus errors in the page table walker Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: Skip checking CSR privilege level in debugger... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	KONRAD Frederic	gdbstub: riscv: fix the fflags registers Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Fix mstatus dirty mask Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Atish Patra	target/riscv: Use both register name and ABI name Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update model and compatible strings... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Remove handcrafted clock nodes for... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Fix broken GEM support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Instantiate OTP memory with a serial... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Implement a model for SiFive FU540 OTP Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Update default bios for sifive_u machine Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Change UART node name in device tree Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update UART base addresses and IRQs Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Reference PRCI clocks in UART and... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Add PRCI block to the SoC Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Generate hfclk and rtcclk nodes Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Implement PRCI model for FU540 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update PLIC hart topology configuration... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update hart configuration to reflect... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Set the minimum number of cpus to 2 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Add a "hartid-base" property to RISC-V... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Extract hart realize to a separate routine Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a sifive_cpu.h to include both E and U cpu... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: Drop sifive_mmio_emulate() Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Update the PRCI register block... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Fix a typo of hfxosccfg register... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Remove the unnecessary include of... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Remove executable attribute of opensbi... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove the unnecessary include of target... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change create_fdt() to return void Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove not needed PLIC properties in device... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Use qemu_fdt_setprop_cell() for property... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove superfluous "linux, phandle" property Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove duplicated "hw/hw.h" inclusion Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_test: Add reset functionality Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hmp: Add a command to show virtual memory mappings Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Resolve full path of the given bios image Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a helper routine for finding firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: rv32: Root page table address can be larger... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Update the Hypervisor CSRs to v0.4 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Create function to test if FP is enabled Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	riscv: plic: Remove unused interrupt functions Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Philippe Mathieu...	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE)... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Philippe Mathieu...	target/riscv/pmp: Restrict priviledged PMP to system... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Guenter Roeck	riscv: sifive_u: Fix clock-names property for ethernet... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Guenter Roeck	riscv: sivive_u: Add dummy serial clock and aliases... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-09-17	Guenter Roeck	riscv: sifive_u: Add support for loading initrd Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-07-26	Alistair Francis	riscv/boot: Fixup the RISC-V firmware warning Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	hw/riscv: Load OpenSBI as the default firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	roms: Add OpenSBI version 0.4 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Extend the kernel loading support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Add support for loading a firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Split out the boot functions Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Update the plic hart config to support... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Wladimir J. van...	disas/riscv: Fix `rdinstreth` constraint Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-27	Michael Clark	disas/riscv: Disassemble reserved compressed encodings... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Atish Patra	riscv: virt: Add cpu-topology DT node. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Jim Wilson	RISC-V: Update syscall list for 32-bit support. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Joel Sing	RISC-V: Clear load reservations on context switch and SC Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Palmer Dabbelt	RISC-V: Add support for the Zicsr extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Palmer Dabbelt	RISC-V: Add support for the Zifencei extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add support for disabling/enabling Counters Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Remove user version information Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Require either I or E base extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Set privledge spec 1.11.0 as default Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add the mcountinhibit CSR Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Add the privledge spec version 1.11.0 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Restructure deprecatd CPUs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Palmer Dabbelt	RISC-V: Fix a memory leak when realizing a sifive_e Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Bin Meng	riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Fix a PMP check with the correct access size Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Fix a PMP bug where it succeeds even if PMP... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Check PMP during Page Table Walks Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Check for the effective memory privilege mode... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Raise access fault exceptions on PMP violations Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Hesham Almatary	RISC-V: Only Check PMP if MMU translation succeeds Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Michael Clark	target/riscv: Implement riscv_cpu_unassigned_access Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Dayeol Lee	target/riscv: Fix PMP range boundary address bug Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
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AR7 emulation for QEMU

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