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2019-09-17	Bin Meng	riscv: sifive: Implement a model for SiFive FU540 OTP Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Update default bios for sifive_u machine Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Change UART node name in device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update UART base addresses and IRQs Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Reference PRCI clocks in UART and... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Add PRCI block to the SoC Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Generate hfclk and rtcclk nodes Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Implement PRCI model for FU540 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update PLIC hart topology configuration... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update hart configuration to reflect... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Set the minimum number of cpus to 2 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Add a "hartid-base" property to RISC-V... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Extract hart realize to a separate routine Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a sifive_cpu.h to include both E and U cpu... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: Drop sifive_mmio_emulate() Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Update the PRCI register block... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Fix a typo of hfxosccfg register... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Remove the unnecessary include of... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Remove executable attribute of opensbi... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove the unnecessary include of target... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change create_fdt() to return void Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove not needed PLIC properties in device... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Use qemu_fdt_setprop_cell() for property... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove superfluous "linux, phandle" property Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove duplicated "hw/hw.h" inclusion Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_test: Add reset functionality Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hmp: Add a command to show virtual memory mappings Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Resolve full path of the given bios image Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a helper routine for finding firmware Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: rv32: Root page table address can be larger... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-08-13	Bin Meng	riscv: roms: Fix make rules for building sifive_u bios Signed-off-by: Bin Meng <bmeng.cn@gmail.com> ...1564812484-20385-1-git-send-email-bmeng.cn@gmail.com	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Update the plic hart config to support... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-06-24	Bin Meng	riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-03-19	Bin Meng	riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-03-19	Bin Meng	riscv: sifive_uart: Generate TX interrupt Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree

AR7 emulation for QEMU

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