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opensbi: Upgrade from v0.4 to v0.5
2019-11-14
Alistair
F
ranci
s
o
p
ensbi:
Upgrade
f
rom v0
.
4 to
v
0
.
5
Palmer Dabbelt
(1):
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@dabbelt.com>
commit
|
commitdiff
|
tree
2019-11-14
Alistai
r
Fr
a
ncis
target/
r
iscv: R
e
move ato
m
i
c
access
e
s to MI
P
CSR
Reviewed-by:
Palmer Dabbelt
<palmer@dabbelt.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@dabbelt.com>
commit
|
commitdiff
|
tree
2019-11-14
hiroyuk
i
.
obinata
r
emove unneces
s
ary ifdef TARGET_RISCV64
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-11-01
P
a
lmer Dabbelt
MAINTAINERS: Chang
e
to my
p
e
rs
o
nal
e
ma
i
l add
r
es
s
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@dabbelt.com>
commit
|
commitdiff
|
tree
2019-10-28
D
ayeol Le
e
target/ris
c
v
: PMP viola
t
ion due to wron
g
size parameter
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Fr
a
ncis
riscv/boot: Fi
x
possible memory l
e
ak
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Jon
a
than Behrens
targe
t
/riscv: Make the priv
register writable by GDB
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Jona
t
ha
n
Behrens
tar
g
et/riscv:
E
xpose "priv" reg
i
ster for GDB
for reads
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Jonathan
B
ehrens
target/riscv:
Tell gdbstub the correct num
b
er of
C
SRs
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
A
listair Franci
s
riscv/virt: Jump to pflash if s
p
ecified
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Alista
i
r Francis
riscv/v
i
rt
:
Add the PFlash CFI01 device
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
s
t
air Francis
ri
s
cv/
v
irt:
M
a
nually def
i
n
e the
m
ac
h
ine
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
stair Francis
riscv
/
s
i
fi
v
e_u: Ad
d
the start-i
n
-flash property
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
riscv/si
f
ive_u: Manu
a
l
ly define the machine
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Franc
i
s
r
iscv/s
i
five_u: Add Q
S
P
I
memory region
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Francis
riscv/sifive_u: Add L2-LIM cache memory
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Giuseppe
M
us
a
cchio
linux-user/riscv: Propagate
f
ault addr
e
ss
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
B
i
n Men
g
r
iscv: s
i
five_u: Add ethernet0
to the
a
l
iases
n
ode
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
B
in M
e
n
g
riscv: hw: Drop "clock-frequ
e
n
cy" property of cpu
no
d
es
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Palmer D
a
bb
e
lt
R
I
SC-V: Impleme
n
t cp
u
_do_tra
n
saction_failed
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Palme
r
Dabbelt
RISC
-
V: Hand
l
e bu
s
err
o
rs
in the page tab
l
e walker
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-10-28
Bi
n
M
eng
ris
c
v: Skip chec
k
i
ng
CSR p
r
i
v
ile
g
e
leve
l
in debugger
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
KONRAD Fre
d
er
i
c
gdbs
t
u
b: r
i
scv:
f
ix the ffla
g
s regist
e
rs
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Ali
s
tair Francis
t
arget/riscv: Use TB_FLA
G
S_MSTATUS_
F
S
for fl
o
ating
.
.
.
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Franci
s
t
a
rget/riscv: Fix mstatus dir
t
y ma
s
k
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Atish
Patra
t
ar
g
et
/
riscv: Use both
r
egister name and ABI name
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Update mod
e
l and c
o
mpatible strings
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u:
Remove h
a
ndcrafted clo
c
k
nodes for
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Fix b
r
o
ken
G
EM support
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
ris
c
v: s
i
five_u
:
Inst
a
nt
i
at
e
OTP me
m
o
ry with a serial
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Implement a model for
SiFive FU5
4
0
O
T
P
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Me
n
g
riscv: roms: Update default
b
io
s
for sifive_u machin
e
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive_u:
C
hang
e
UART node name in device tree
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifive_u: Up
d
ate UART ba
s
e a
d
dr
e
sses and IRQs
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
c
v
: s
i
f
i
v
e
_
u: Reference PRCI clocks i
n
UART
and
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifiv
e
_u: Add PR
C
I block to the SoC
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sif
i
ve_u: Generate hfclk and rtcclk nodes
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifive: Implement PRC
I
model for FU
5
40
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sifive_u: Update PLIC har
t
topology
configu
r
a
tion
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
M
eng
risc
v
: si
f
ive_u: Update
h
art conf
i
guration t
o
reflect
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
riscv: s
i
fiv
e
_u: Se
t
the
min
i
m
um
n
umbe
r
of
c
p
us to 2
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
e
ng
riscv: har
t
: A
d
d
a "hartid-base" property to R
I
S
C-V
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: hart: Extrac
t
hart realize to a separ
a
te routine
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v:
Add
a sifive_cpu
.
h to include both E and U cpu
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Meng
riscv: sifive_e: Drop sifive_m
m
io_emulate()
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
sifiv
e
_
e:
prci: Upda
t
e
t
he PR
C
I regist
e
r block
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
risc
v
: si
f
ive_e: prci: Fix a ty
p
o
of hfxosccfg
regist
e
r
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
sifi
v
e: Rename sifi
v
e_prci
.
{c, h} to sifive_e_pr
c
i
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifive_u: Remove t
h
e
u
nnec
e
ssary inclu
d
e o
f
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: roms:
R
e
move
exe
c
utable att
r
i
bute of ope
n
sbi
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Me
n
g
r
i
scv: hw: Remove the unnecessary include of target
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
r
i
scv
:
hw: Change
t
o
use qem
u
_
log_mas
k
(LO
G
_
GUEST_ERROR
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: hw: Chan
g
e create
_
fdt(
)
to return void
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
hw: Remove not
ne
e
ded PLIC
properties in device
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
r
i
s
c
v
: hw: Us
e
qemu_fdt_setprop_cell
(
)
f
o
r prope
r
ty
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv:
h
w
: Remov
e
sup
e
rfl
u
ous "linux, ph
a
ndle" property
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
ng
ris
c
v: hw: Remove duplicated "hw/hw
.
h" in
c
lusion
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive_
t
e
st: Add reset
functionality
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: hmp
:
Add a command to show virtual
memory ma
p
pings
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv:
R
esolve full path of th
e
give
n
bios
i
mage
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: Add a he
l
p
e
r routine for f
i
n
ding firmware
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: rv32: Root p
a
g
e
table ad
d
ress
can be la
r
ge
r
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair
F
ranci
s
target/riscv: Update the Hy
p
erviso
r
CSRs t
o
v0
.
4
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Alista
i
r Francis
t
arg
e
t/riscv: Create func
t
ion to tes
t
if
FP is enabled
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Alist
a
ir Francis
ris
c
v:
plic: Remove unu
s
e
d interrupt functio
n
s
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Phi
l
ippe
M
athi
e
u
.
.
.
t
a
r
get/risc
v
/pmp: Convert qemu_l
o
g_mask(L
O
G_T
R
ACE)
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Ph
i
lip
p
e Mathieu
.
.
.
targe
t
/ri
s
cv/pmp: Restrict priviledged PM
P
to system
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Guen
t
er Roeck
riscv:
si
f
i
ve_u:
F
ix c
l
ock-names property for ethe
r
net
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Guen
t
er Roeck
riscv: sivive_u
:
Add
d
ummy serial clo
c
k and aliases
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-09-17
Gue
n
ter
R
o
e
ck
riscv: sifive_u: A
d
d support fo
r
lo
a
d
i
ng in
i
trd
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-07-26
Alistai
r
Francis
riscv/boot:
F
ixup the RISC-
V
f
i
rmw
a
re warning
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-07-18
Alis
t
air Francis
hw
/
risc
v
: Load OpenSBI as the
d
e
fault firmware
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-07-18
Alistair
Franc
i
s
roms: Add OpenSBI v
e
rsion
0
.
4
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-27
Alistair Francis
hw
/
risc
v
: Exten
d
the kernel loading sup
p
ort
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-27
Alistair Francis
hw/
r
is
c
v: Add su
p
port for loading a firmware
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
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tree
2019-06-27
Alistai
r
Fra
n
cis
h
w/ri
s
cv: Split out the boot functions
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
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tree
2019-06-27
Bin Men
g
riscv: sifive_u
:
Update th
e
pl
i
c hart
c
o
nfig to s
u
p
port
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
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tree
2019-06-27
B
in Meng
riscv:
sifiv
e
_u: Do
not create hard-coded pha
n
dles
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-27
Wl
a
dimir J
.
va
n
.
.
.
disas/ris
c
v:
Fix `rdinstreth` cons
t
rain
t
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
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tree
2019-06-27
Michae
l
Clark
disas/
r
isc
v
: Disassem
b
le reserv
e
d compress
e
d encodin
g
s
.
.
.
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-26
Atish Patr
a
riscv: vi
r
t: Add cpu-t
o
p
o
logy DT node
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-26
Jim W
i
lson
R
I
S
C
-
V: Update syscal
l
l
i
st for
3
2
-
bit
support
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-26
Joel Sing
RISC-V: C
l
ear load rese
r
vations on context swi
t
c
h a
n
d
S
C
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-26
Palmer Dabbelt
RISC-V
:
Add support
fo
r
the Zics
r
extension
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-26
Palmer Dabbelt
RISC-V: Add suppor
t
fo
r
th
e
Zifencei ext
e
nsion
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
tar
g
e
t
/riscv:
A
d
d support
for disabl
i
ng/enabling Co
u
n
ters
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alist
a
ir Francis
ta
r
get/riscv: Remov
e
us
e
r version in
f
ormat
i
on
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
t
a
r
g
e
t/riscv: Req
u
ire either
I or E base extensi
o
n
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Franci
s
qemu-deprecated
.
texi: Deprecat
e
the RI
S
C-V privledge
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alista
i
r
Franc
i
s
target/
r
iscv:
Set
privl
e
dge spec
1
.
11
.
0 as default
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
t
arget/ri
s
cv:
Add
the mcountin
h
ib
i
t CSR
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
A
lista
i
r
Franci
s
target
/
riscv: Ad
d
t
h
e privledge spec
vers
i
o
n
1
.
11
.
0
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Ali
s
tair Fran
c
is
target/riscv: Restruc
t
ure
d
eprecatd CPUs
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Palmer Dabbelt
RISC-V: Fix a mem
o
ry leak when realizi
n
g a sifive
_
e
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Bin Meng
ri
s
cv: virt: Correct p
c
i "bus-range" e
n
c
oding
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Hesham Almatary
R
I
SC
-
V
: Fix a PMP che
c
k with the correct access size
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Hesha
m
Almata
r
y
R
ISC-V
:
Fix a PMP
bug
where it succeeds even if
P
MP
.
.
.
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
H
e
s
h
am Almatary
R
I
SC-V: Check
P
M
P
d
uring
P
age T
a
ble W
a
l
ks
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Hesh
a
m
A
lmata
r
y
RISC-V: Check for the
e
ff
e
cti
v
e me
m
o
r
y privile
g
e mode
.
.
.
Reviewed-by:
Palmer Dabbelt
<palmer@sifive.com>
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
H
e
s
h
a
m
Almata
r
y
RISC-V:
R
ais
e
a
c
cess fault
exceptions
o
n PMP violation
s
Signed-off-by:
Palmer Dabbelt
<palmer@sifive.com>
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|
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