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hw/net/can: ZynqMP CAN device requires PTIMER
2021-02-03 Philippe Mathieu... hw/net/can: ZynqMP CAN device requires PTIMER
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131184449.382425-6-f4bug@amsat.org
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2021-02-03 Philippe Mathieu... hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131184449.382425-5-f4bug@amsat.org
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2021-02-03 Philippe Mathieu... hw/arm/xlnx-versal: Versal SoC requires ZDMA
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131184449.382425-4-f4bug@amsat.org
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2021-02-03 Philippe Mathieu... hw/arm/exynos4210: Add missing dependency on OR_IRQ
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131184449.382425-3-f4bug@amsat.org
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2021-02-03 Philippe Mathieu... hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131184449.382425-2-f4bug@amsat.org
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2021-02-02 Philippe Mathieu... hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210131103401.217160-1-f4bug@amsat.org
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2021-02-02 Philippe Mathieu... hw/ssi: imx_spi: Rework imx_spi_write() to handle block...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210115153049.3353008-6-f4bug@amsat.org>
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2021-02-02 Philippe Mathieu... hw/ssi: imx_spi: Rework imx_spi_read() to handle block...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210115153049.3353008-5-f4bug@amsat.org>
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2021-02-02 Philippe Mathieu... hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-02-02 Philippe Mathieu... hw/ssi: imx_spi: Remove pointless variable initialization
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210115153049.3353008-3-f4bug@amsat.org>
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2021-01-29 Philippe Mathieu... target/arm: Replace magic value by MMU_DATA_LOAD definition
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210127232822.3530782-1-f4bug@amsat.org
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2021-01-27 Philippe Mathieu... tcg/tci: Restrict tci_write_reg16() to 64-bit hosts
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210123094107.2340222-1-f4bug@amsat.org>
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2021-01-26 Philippe Mathieu... gitlab-ci: Test building linux-user targets on CentOS 7
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210121172829.1643620-3-f4bug@amsat.org>
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2021-01-26 Philippe Mathieu... tests/docker: Install static libc package in CentOS 7
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210121172829.1643620-2-f4bug@amsat.org>
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2021-01-23 Philippe Mathieu... accel/tcg: Restrict cpu_io_recompile() from other accelerators
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210117164813.4101761-6-f4bug@amsat.org>
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2021-01-23 Philippe Mathieu... accel/tcg: Declare missing cpu_loop_exit*() stubs
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210117164813.4101761-5-f4bug@amsat.org>
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2021-01-23 Philippe Mathieu... accel/tcg: Restrict tb_gen_code() from other accelerators
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210117164813.4101761-4-f4bug@amsat.org>
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2021-01-23 Philippe Mathieu... accel/tcg: Make cpu_gen_init() static
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210117164813.4101761-2-f4bug@amsat.org>
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2021-01-23 Philippe Mathieu... softmmu/physmem: Silence GCC 10 maybe-uninitialized...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210117170411.4106949-1-f4bug@amsat.org>
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2021-01-19 Philippe Mathieu... target/arm/m_helper: Silence GCC 10 maybe-uninitialized...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210119062739.589049-1-f4bug@amsat.org
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2021-01-18 Philippe Mathieu... shippable.yml: Remove jobs duplicated on Gitlab-CI
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210108145103.269353-1-f4bug@amsat.org>
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2021-01-18 Philippe Mathieu... tests/docker: Remove Debian 9 remnant lines
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210107072933.3828450-1-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... docs/system: Remove deprecated 'fulong2e' machine alias
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210106184602.3771551-1-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove vendor specific CPU definitions
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210112210152.2072996-4-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove CPU_NANOMIPS32 definition
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210112210152.2072996-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove CPU_R5900 definition
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210112210152.2072996-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 LL/SC opcodes to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208203704.243704-14-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208203704.243704-13-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208203704.243704-12-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208203704.243704-11-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208203704.243704-10-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 COP1X opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Convert Rel6 Special2 opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove now unreachable LSA/DLSA opcodes...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Introduce decodetree helpers for Release6...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-24-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Introduce decodetree helpers for MSA LSA...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-23-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract LSA/DLSA translation generators
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-22-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Use decode_ase_msa() generated from decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-21-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Introduce decode tree bindings for MSA ASE
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-20-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Pass TCGCond argument to MSA gen_check_zero_ele...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-25-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract MSA translation routines
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201120210844.2625602-5-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Declare gen_msa/_branch() in 'translate.h'
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-18-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract MSA helper definitions
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201120210844.2625602-4-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract MSA helpers from op_helper.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201123204448.3260804-5-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Move msa_reset() to msa_helper.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201215225757.764263-15-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-10-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove CPUMIPSState* argument from gen_msa...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-9-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract msa_translate_init() from mips_tcg_init()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-8-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Alias MSA vector registers on FPU scalar...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-7-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove now unused ASE_MSA definition
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-6-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Simplify MSA TCG logic
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-5-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-4-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Simplify msa_reset()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Introduce ase_msa_available() helper
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201208003702.4088927-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/translate: Expose check_mips_64() to 32...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/translate: Extract decode_opc_legacy()...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Only build TCG code when CONFIG_TCG is set
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201206233949.3783184-20-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract FPU specific definitions to translate.h
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201214183739.500368-16-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Declare generic FPU / Coprocessor functions...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201214183739.500368-15-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Replace gen_exception_end(EXCP_RI) by...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201214183739.500368-12-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Replace gen_exception_err(err=0) by gen_excepti...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201214183739.500368-11-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/translate: Add declarations for generic...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201207235539.4070364-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/translate: Extract DisasContext structure
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201207235539.4070364-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Rename translate_init.c as cpu-defs.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201214183739.500368-10-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Move mmu_init() functions to tlb_helper.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201206233949.3783184-15-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Fix code style for checkpatch.pl
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201206233949.3783184-14-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Rename helper.c as tlb_helper.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201206233949.3783184-13-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Move common helpers from helper.c to cpu.c
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214183739.500368-5-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Add !CONFIG_USER_ONLY comment after #endif
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Extract FPU helpers to 'fpu_helper.h'
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201120210844.2625602-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Inline cpu_state_reset() in mips_cpu_reset()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214183739.500368-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-16-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-15-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-14-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-13-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-12-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Use ISA_MIPS32R6 definition...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-11-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Use ISA_MIPS32R5 definition...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-10-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Use ISA_MIPS32R3 definition...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-9-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Use ISA_MIPS32R2 definition...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-8-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Use ISA_MIPS32 definition to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-7-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-6-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-5-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Rename CPU_MIPSxx Release 1...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-4-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Reorder CPU_MIPS5 definition
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210104221154.3127610-2-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Replace CP0_Config0 magic values by proper...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201201132817.2863301-3-f4bug@amsat.org>
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2021-01-14 Philippe Mathieu... target/mips: Add CP0 Config0 register definitions for...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201201132817.2863301-2-f4bug@amsat.org>
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2021-01-13 Philippe Mathieu... decodetree: Open files with encoding='utf-8'
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210110000240.761122-1-f4bug@amsat.org>
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2021-01-12 Philippe Mathieu... target/i386: Use X86Seg enum for segment registers
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210109233427.749748-1-f4bug@amsat.org>
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2021-01-11 Philippe Mathieu... util/oslib-win32: Fix _aligned_malloc() arguments order
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210111001606.1122983-1-f4bug@amsat.org>
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2021-01-06 Philippe Mathieu... tests/docker: Include 'ccache' in Debian base image
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201213211601.253530-1-f4bug@amsat.org>
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2021-01-06 Philippe Mathieu... hw/timer/slavio_timer: Allow 64-bit accesses
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201205150903.3062711-1-f4bug@amsat.org>
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2021-01-04 Philippe Mathieu... hw/pci-host/bonito: Use pci_config_set_interrupt_pin()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201231224911.1467352-5-f4bug@amsat.org>
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2021-01-04 Philippe Mathieu... hw/pci-host/bonito: Display hexadecimal value with...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201231224911.1467352-3-f4bug@amsat.org>
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2021-01-04 Philippe Mathieu... hw: Use the PCI_DEVFN() macro from 'hw/pci/pci.h'
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20201231224911.1467352-4-f4bug@amsat.org>
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2021-01-04 Philippe Mathieu... hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h'
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-01-04 Philippe Mathieu... hw/pci-host/uninorth: Use the PCI_FUNC() macro from...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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AR7 emulation for QEMU