| commit | 5f89ce4fc2afdb81eaed90f337d7016207a2b176 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Wed, 16 Dec 2020 11:30:11 +0000 (16 12:30 +0100) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Thu, 14 Jan 2021 16:13:53 +0000 (14 17:13 +0100) | ||
| tree | 383b4c95f4046d444984451a7350b97afd551ab2 | treesnapshot (tar.gz zip) |
| parent | bae4b15aa4fa56815e08cee395486a1c990caa99 | commitdiff |
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
| target/mips/mips-defs.h | diffblobblamehistory | |
| target/mips/translate.c | diffblobblamehistory |