| commit | 8b0ea9b638adadcf056f4a18fe53a7c6339beba8 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Wed, 16 Dec 2020 22:59:07 +0000 (16 23:59 +0100) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Thu, 14 Jan 2021 16:13:53 +0000 (14 17:13 +0100) | ||
| tree | 25b77517bdd13f095f26af114b92b725f85c6b44 | treesnapshot (tar.gz zip) |
| parent | bf5523773eac7a17cf6f6a062b3311a09063881f | commitdiff |
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
| target/mips/mips-defs.h | diffblobblamehistory | |
| target/mips/translate_init.c.inc | diffblobblamehistory |