| commit | 72f31f60f829980ad22da8049bb41af0dc49c3f4 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sun, 29 Nov 2020 22:57:02 +0000 (29 23:57 +0100) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Thu, 14 Jan 2021 16:13:53 +0000 (14 17:13 +0100) | ||
| tree | d9a81235b2335628f46381ba6673f8bab35993ef | treesnapshot (tar.gz zip) |
| parent | 25a1362875874936c185eba72203de6e9581251e | commitdiff |
target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
| target/mips/cpu-defs.c.inc | diffblobblamehistory | |
| target/mips/cpu.c | diffblobblamehistory |