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MAINTAINERS: Update 9pfs tree URL
2021-01-16
Alist
a
ir F
r
anc
i
s
r
iscv: Pass RISCVHartArrayS
t
ate by
p
ointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Franci
s
riscv/o
p
entitan: Update
the OpenTitan mem
o
r
y
layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
F
ranc
i
s
hw/r
i
scv: U
s
e the CP
U
to determine i
f
32
-
bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Fra
n
c
i
s
targe
t
/riscv: cpu: Se
t
XL
E
N
inde
p
enden
t
ly from target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
s
t
air Francis
t
a
rget/riscv: csr
:
Remove co
m
pile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lista
i
r Franc
i
s
ta
r
ge
t
/
r
i
scv: cpu_
h
e
lper: Remove co
m
pile time XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
tair Franc
i
s
target/riscv
:
cpu: Remove compile
t
ime X
L
EN c
h
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Fra
n
c
i
s
target/riscv: Specify the X
L
EN for CP
U
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
a
ncis
target/risc
v
: Add a
riscv_cp
u
_is_
3
2bit
(
) h
e
lper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/ris
c
v: f
p
u_h
e
l
pe
r
: Match function defs i
n
H
E
LPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Fran
c
is
hw/ris
c
v: sifive_u: Remove compile
t
ime XL
E
N checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
stair
Francis
hw/riscv: spike: Remove compile time XLE
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r
F
ra
n
cis
hw/riscv: virt: Remov
e
compil
e
time XLEN ch
e
c
ks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Fra
n
c
is
hw/r
i
s
cv: boot:
Remove compile time XLEN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
s
t
a
i
r
Francis
riscv: virt: Remove ta
r
g
et mac
r
o
co
n
di
t
io
n
als
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Francis
r
iscv: spike: Remo
v
e t
a
rget macro conditi
o
nals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stai
r
Francis
target/
r
iscv: Add a TYPE
_
R
I
S
C
V_CPU
_
BASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
r
anc
i
s
hw/riscv: E
x
pand
t
he is
3
2-
b
it chec
k
to su
p
por
t
more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Francis
i
nt
c
/ib
e
x_plic: Clear
i
n
terrupts that occur dur
i
ng
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alistair F
r
a
n
c
is
r
egister: Rem
o
ve
u
nnecessary NULL chec
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Al
i
s
t
air Franci
s
intc/ibex_plic
:
Ensure we don't loose interr
u
pts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistai
r
F
rancis
in
t
c/
i
bex_
p
lic: Fix some
t
y
pos in
t
h
e
comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
hw/intc/i
b
e
x_plic: Clear the
claim register
w
hen read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Fran
c
is
targ
e
t
/
riscv: Spl
i
t the Hypervisor execute lo
a
d
h
elpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
F
rancis
target/riscv: Remove t
h
e h
y
p l
o
ad and stor
e
func
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
target/ris
c
v: Remove the HS_TWO_
S
TA
G
E flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alista
i
r Francis
target/riscv:
S
et
t
h
e virtualised MMU
m
o
d
e when doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
F
rancis
t
a
r
ge
t
/riscv: Add a virtuali
s
ed
MMU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alista
i
r Fr
a
ncis
l
in
u
x-user/sys
c
all: Fix mi
s
sing target_
t
o_host_timespec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Fran
c
i
s
hw/riscv: Load the
k
e
r
nel afte
r
the fi
r
mware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Fra
n
cis
h
w
/riscv: Add a riscv
_
is_32_bit
(
) func
t
io
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alis
t
a
ir Franci
s
hw/riscv: Return the end address of the
l
o
aded firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
listair Francis
hw/riscv: sifive_u: Allow
spec
i
fying the CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tair Francis
riscv: Convert interrupt logs to use
q
em
u
_log_mask
(
)
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
l
istair Francis
c
ore/register:
S
p
e
cify i
n
s
t
a
nc
e
_size in the TypeInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv: Sup
p
ort the Virtu
a
l Instruction fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Francis
target/r
i
scv
:
Return the exception from
i
nv
a
l
i
d
C
SR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r
F
r
a
ncis
target/riscv: Support the v0
.
6 Hyp
e
rvi
s
o
r
extension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair
F
ra
n
cis
t
a
rget/riscv: Onl
y
support
little endian
g
u
e
s
t
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair F
r
ancis
target/
r
iscv: Only
support
a
single VSXL
l
ength
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
target/riscv: Update the CSRs to the
v0
.
6 H
y
p extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stair Francis
targ
e
t/risc
v
: Update the Hype
r
visor trap retu
r
n/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Francis
target/riscv: Fix t
h
e inter
r
upt
c
ause code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
tar
g
et/riscv: Convert MS
T
AT
U
S MTL to GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/risc
v
: Don
'
t allow
guest to write to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
Francis
t
a
rget
/
r
i
scv: Do t
w
o-stag
e
look
u
ps on hlv/hl
v
x/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Fra
n
ci
s
target/ris
c
v: Allow generating hlv/h
l
vx/h
s
v instruction
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
ir Fra
n
cis
t
arget/riscv: Allow settin
g
a
two-stage lookup in
the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc: ibex_plic: Honour source
p
riorities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
h
w/i
n
t
c
:
i
b
ex_plic: D
o
n
'
t allow repeat interrupts o
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/i
n
tc: ibex_plic:
U
pdate
t
he pend
i
ng ir
q
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
A
listair
F
rancis
hw/sd/pl181: Replace fprin
t
f
(
stder
r
, "*\
n
") with error_report()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Ali
s
tair Francis
hw/char: Con
v
er
t
the Ibex UART to use
the registerf
i
elds
A
PI
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Al
i
s
t
air
F
r
a
nci
s
hw
/
char: Conv
e
rt the Ibex
U
ART to use the qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Francis
hw/ri
s
cv: All
o
w 64 bit access t
o
SiFive CLI
N
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
a
ncis
target/ris
c
v:
U
se a smaller guess size for
no-MMU P
M
P
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
ran
c
is
r
is
c
v/
o
pentitan: Connect
t
he UA
R
T d
e
vice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
rancis
riscv/opentitan: C
o
n
nect the PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair
F
r
a
ncis
hw/intc
:
Initial commit
o
f
l
owRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
hw/
c
har: Initial c
o
mmi
t
of
I
bex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
riscv/o
p
entitan
:
F
i
x the ROM
s
iz
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franci
s
targe
t
/riscv: Implement checks for h
f
e
n
ce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Fra
n
c
is
target/riscv:
Move the h
f
ence instruct
i
ons to the r
v
h
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
targ
e
t/riscv: Report errors
validating
2
n
d
-stage PTE
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
target/riscv: Set access as
d
a
ta
_
load when valida
t
ing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
sifive_
e
:
Support
t
he revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv: Init
i
a
l
commit of OpenTitan machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistai
r
F
rancis
targ
e
t/riscv: Add the lowRISC Ib
e
x C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Francis
target/riscv
:
Don't set PMP feat
u
r
e
in the cpu
init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fra
n
cis
tar
g
e
t
/riscv: Disable the
MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
target/
r
isc
v
:
D
on't overwri
t
e the
r
eset
v
ector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
s
t
a
i
r Francis
riscv/boot: Add a missing header in
c
lud
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
an
c
is
riscv: sifive_e: Manually define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franci
s
d
oc
s
: d
e
preca
t
ed: Update the
-b
i
os d
o
cumen
t
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alis
t
air
F
rancis
target
/
riscv: D
r
op support for ISA spec
ver
s
ion
1
.
0
9
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
ist
a
ir Fran
c
is
targe
t
/riscv: Remove the
d
epre
c
ated CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
listair F
r
anci
s
hw/riscv: spike
:
R
emove depre
c
ated ISA
s
pecific
m
achi
n
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Fran
c
is
riscv: AN
D
stage-1 and stage-2 protect
i
on
f
l
ags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair
Francis
riscv
:
Don't use stag
e
-
2 PTE
lookup protection flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alis
t
air Francis
riscv/si
f
ive
_
u:
A
dd
a serial property to the
si
f
iv
e
_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
listair
Francis
riscv/sifiv
e
_
u
: Fix up fil
e
orde
r
ing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alistair Fra
n
c
i
s
linux-user: Support
fut
e
x_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alis
t
ai
r
Francis
linux-user/
r
isc
v
: Update the syscall_nr's to th
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair Francis
l
in
u
x-user/syscall: Add suppor
t
for clock_getti
m
e64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Ali
s
tair F
r
ancis
linux-user: Protect m
o
re s
y
scalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-03-17
A
lista
i
r
Franc
i
s
targ
e
t/ri
s
cv:
C
orrectly implement TSR
t
rap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
list
a
ir Fr
a
n
c
is
target/risc
v
:
A
llow
ena
b
ling the H
y
per
v
isor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
listai
r
F
rancis
target/riscv: Add the MST
A
TUS_MPV_ISSET helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Franc
i
s
targe
t
/riscv: Add sup
p
or
t
for the 32-b
i
t MST
A
T
USH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
listair Francis
t
a
rget/ris
c
v: Se
t
h
tv
a
l and mtval2 on execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alis
t
ai
r
Fr
a
ncis
tar
g
e
t
/riscv: Raise the ne
w
execption
s
when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Ali
s
tair Francis
ta
r
get/riscv: Imp
l
ement s
e
c
o
n
d
stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Franci
s
ta
r
get
/
riscv: All
o
w specifyi
n
g
MM
U
s
t
age
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
listair Francis
target/
r
iscv: Respect MPRV and
SP
R
V for
f
loa
t
in
g
p
o
int ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
target/ri
s
c
v
:
M
ark both sstatus and mss
t
atus_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
targ
e
t/riscv: Disable gu
e
s
t FP suppo
r
t b
a
sed on vi
r
tual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
target/r
i
s
cv: Only set TB flags
with FP
s
t
atus if enabl
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair
F
ran
c
is
targ
e
t/risc
v
:
Remove the
hre
t
i
ns
t
ruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alis
t
air Franci
s
target/ris
c
v: Add hf
e
nce
i
ns
t
ructi
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
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2020-02-27
Alist
a
ir F
r
a
ncis
target/riscv: Add Hypervis
o
r
trap return sup
p
ort
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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