Public Git Hosting - qemu/ar7.git/search

2021-03-09	Bin Meng	hw/ppc: e500: Add missing <ranges> in the eTSEC node Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-09	Bin Meng	hw/net: fsl_etsec: Fix build error when HEX_DUMP is on Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: virt: Map high mmio for PCIe Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: virt: Limit RAM size in a 32-bit system Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: Drop 'struct MemmapEntry' Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	docs/system: riscv: Add documentation for sifive_u... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	docs/system: Add RISC-V documentation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	docs/system: Sort targets in alphabetical order Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: sifive_u: Add QSPI2 controller and connect... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/riscv: sifive_u: Add QSPI0 controller and connect... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/ssi: Add SiFive SPI controller support Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/block: m25p80: Add various ISSI flash information Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/block: m25p80: Add ISSI SPI flash support Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	roms/opensbi: Upgrade from v0.8 to v0.9 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	hw/misc: sifive_u_otp: Use error_report() when block... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-03-04	Bin Meng	target/riscv: Declare csr_ops[] with a known size Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-21	Bin Meng	hw/mips: loongson3: Drop 'struct MemmapEntry' Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sdhci: Simplify updating s->prnsts in sdhci_sdma_tran... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Bypass the RCA check for CMD13 in SPI mode Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Skip write protect groups check in CMD24... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Skip write protect groups check in sd_erase... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Move the sd_block_{read, write} and macros... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Fix CMD30 response type Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Only SDSC cards support CMD28/29/30 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Fix address check in sd_erase() Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Handle the rest commands with R1b response... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Fix STOP_TRANSMISSION (CMD12) response Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Fix SEND_IF_COND (CMD8) response Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Support multiple block write Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Support single block write Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: Introduce receive_ready() callback Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Allow single/multiple block write for SPI... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: sd: Remove duplicated codes in single/multiple... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-19	Bin Meng	hw/sd: ssi-sd: Support multiple block read Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-11	Bin Meng	hw/block/nvme: Fix a build error in nvme_get_feature() Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-10	Bin Meng	target/ppc: Add E500 L2CSR0 write helper Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-10	Bin Meng	hw/net: fsl_etsec: Reverse the RCTRL.RSF logic Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-10	Bin Meng	hw/ppc: e500: Fill in correct <clock-frequency> for... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-10	Bin Meng	hw/ppc: e500: Use a macro for the platform clock frequency Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-02	Bin Meng	hw/ssi: imx_spi: Correct tx and rx fifo endianness Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-02	Bin Meng	hw/ssi: imx_spi: Correct the burst length > 32 bit... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-02	Bin Meng	hw/ssi: imx_spi: Round up the burst length to be multiple... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-02	Bin Meng	hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-02-02	Bin Meng	hw/ssi: imx_spi: Use a macro for number of chip selects... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-25	Bin Meng	net: checksum: Introduce fine control over checksum... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: sd.h: Cosmetic change of using spaces Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: ssi-sd: Use macros for the dummy value and tokens... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: ssi-sd: Add a state representing Nac Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: ssi-sd: Suffix a data block with CRC16 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	util: Add CRC16 (CCITT) calculation routines Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: sd: Drop sd_crc16() Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: sd: Support CMD59 for SPI mode Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-24	Bin Meng	hw/sd: ssi-sd: Fix incorrect card response sequence Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	target/riscv: Remove built-in GDB XML files for CSRs Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	target/riscv: Generate the GDB XML file for CSR registers... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	target/riscv: Add CSR name in the CSR function table Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	target/riscv: Make csr_ops[CSR_TABLE_SIZE] external Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-16	Bin Meng	hw/block: m25p80: Don't write to flash if write is... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-08	Bin Meng	docs/system: arm: Add sabrelite board description Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-08	Bin Meng	hw/arm: sabrelite: Connect the Ethernet PHY at address 6 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-08	Bin Meng	hw/msic: imx6_ccm: Correct register value for silicon... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2021-01-08	Bin Meng	hw/misc: imx6_ccm: Update PMU_MISC0 reset value Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-12-10	Bin Meng	target/i386: seg_helper: Correct segment selector nullificat... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-17	Bin Meng	hw/sd: Fix 2 GiB card CSD register values Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Hook the I2C1 controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Correct DDR memory map Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Map the reserved memory... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Connect the SYSREG module Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/misc: Add Microchip PolarFire SoC SYSREG module... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Connect the IOSCB module Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/misc: Add Microchip PolarFire SoC IOSCB module support Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Connect DDR memory controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/misc: Add Microchip PolarFire SoC DDR Memory Controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-11-03	Bin Meng	hw/riscv: microchip_pfsoc: Document where to look at... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-10-26	Bin Meng	hw/sd/sdcard: Zero out function selection fields before... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-10-22	Bin Meng	hw/intc: Move sifive_plic.h to the include directory Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Sort the Kconfig options in alphabetical... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Drop CONFIG_SIFIVE Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Always build riscv_hart.c Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_test model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_uart model to hw/char Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move riscv_htif model to hw/char Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_plic model to hw/intc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_clint model to hw/intc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_gpio model to hw/gpio Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_u_otp model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_u_prci model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Move sifive_e_prci model to hw/misc Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: sifive_u: Connect a DMA controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: clint: Avoid using hard-coded timebase frequency Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Hook GPIO controllers Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/arm: xlnx: Set all boards' GEM 'phy-addr' property... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/net: cadence_gem: Add a new 'phy-addr' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect a DMA controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/dma: Add SiFive platform DMA controller emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
next

AR7 emulation for QEMU

RSS Atom