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target/riscv: misa to ISA string conversion fix
2022-04-22 Tsukasa OItarget/riscv: misa to ISA string conversion fix
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Weiwei Litarget/riscv: optimize helper for vmv<nr>r.v
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Weiwei Litarget/riscv: optimize condition assign for scale < 0
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Bin Mengtarget/riscv: Add initial support for the Sdtrig extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: Allow software access to MIP SEIP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Enable privileged spec version 1.12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add *envcfg* CSRs support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add support for mconfigptr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Introduce privilege version field in...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add the privileged spec version 1.12.0
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Define simpler privileged spec version...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Wilfred Mallawariscv: opentitan: Connect opentitan SPI Host
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Wilfred Mallawahw/ssi: Add Ibex SPI device model
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-31 Yueh-Ting (eop)... target/riscv: rvv: Add missing early exit condition...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-31 Palmer Dabbelttarget/riscv: Avoid leaking "no translation" TLB entries
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: expose zfinx, zdinx, zhinx{min} properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: add support for zhinx/zhinxmin
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: add support for zdinx
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: add support for zfinx
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: hardwire mstatus.FS to zero when enable...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Weiwei Litarget/riscv: add cfg properties for zfinx, zdinx and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Wilfred Mallawahw: riscv: opentitan: fixup SPI addresses
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Anup Patelhw/riscv: virt: Increase maximum number of allowed...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Anup Pateldocs/system: riscv: Document AIA options for virt machine
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2022-03-03 Anup Patelhw/riscv: virt: Add optional AIA IMSIC support to virt...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Anup Patelhw/intc: Add RISC-V AIA IMSIC device emulation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Anup Patelhw/riscv: virt: Add optional AIA APLIC support to virt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-03 Philipp Tomsichtarget/riscv: fix inverted checks for ext_zb[abcs]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Yu Lidocs/system: riscv: Update description of CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Weiwei Litarget/riscv: add support for svpbmt extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Weiwei Litarget/riscv: add support for svinval extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Weiwei Litarget/riscv: add support for svnapot extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Weiwei Litarget/riscv: add PTE_A/PTE_D/PTE_U bits check for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Guo Rentarget/riscv: Ignore reserved bits in PTE for RV64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Patelhw/intc: Add RISC-V AIA APLIC device emulation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Allow users to force enable AIA CSRs...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Patelhw/riscv: virt: Use AIA INTC compatible string when...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA IMSIC interface CSRs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA xiselect and xireg CSRs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA mtopi, stopi, and vstopi...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA interrupt filtering CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA hvictl and hviprioX CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA CSRs for 64 local interrupts...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement AIA local interrupt priorities
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Allow AIA device emulation to set ireg...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Add defines for AIA CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Add AIA cpu feature
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Allow setting CPU feature from machine...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Improve delivery of guest external interrupts
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement hgeie and hgeip CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Implement SGEIP bit in hip and hie CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Anup Pateltarget/riscv: Fix trap cause for RV32 HS-mode CSR access...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 LIU Zhiweitarget/riscv: Fix vill field write in vtype
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: add a MAINTAINERS entry for XVentanaCondOps
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: Add XVentanaCondOps custom extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: iterate over a table of decoders
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: access cfg structure through DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: access configuration through cfg_ptr...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: riscv_tr_init_disas_context: copy pointer...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: refactor (anonymous struct) RISCVCPU...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Frédéric Pétrottarget/riscv: correct "code should not be reached"...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Petr TesarikAllow setting up to 8 bytes with the generic loader
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Wilfred Mallawainclude: hw: remove ibex_plic.h
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax UXL field for debugging
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Enable uxl field write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Set default XLEN for hypervisor
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vector address with mask
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Fix check range for first fault only
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Remove VILL field in VTYPE
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vsetvl according to XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Split out the vill from vtype
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Split pm_enabled into mask and base
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Alloc tcg global for cur_pm[mask|base]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create current pm fields in env
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax debug check for pm write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Use gdb xml according to max mxlen
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Extend pc for runtime pc write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Ignore the pc bits above XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create xl field in env
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend pc for different XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend link reg for jal and jalr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Don't save pc when exception return
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust pmpcfg access with mxl
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelroms/opensbi: Remove ELF images
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelhw/riscv: Remove macros for ELF BIOS image names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelhw/riscv: spike: Allow using binary firmware as bios
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve32f extension to be...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for narrowing...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for widening...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for single...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for scalar...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for configuration...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve64f extension to be...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for narrowing...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for widening...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU