target/riscv: add support for zhinx/zhinxmin
commita2464a4cec4740c3703d8232f695d6643e0e086e
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 11 Feb 2022 04:39:19 +0000 (11 12:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 3 Mar 2022 03:14:50 +0000 (3 13:14 +1000)
treebb0e33d7341975513b60de76c48850bb4e19be51
parent026e73fa2665f07d24bb715f2c405c3e38587812
target/riscv: add support for zhinx/zhinxmin

  - update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
  - update half float point register read/write
  - disable nanbox_h check

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/fpu_helper.c
target/riscv/helper.h
target/riscv/insn_trans/trans_rvzfh.c.inc
target/riscv/internals.h