| commit | ac4b0302b0ca986a759538f453b44037c7b66dd9 | |
| author | Anup Patel <anup.patel@wdc.com> | |
| Fri, 4 Feb 2022 17:46:51 +0000 (4 23:16 +0530) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 16 Feb 2022 02:24:19 +0000 (16 12:24 +1000) | ||
| tree | ef7311e05b51711e5b3136eef78298a3af85dff1 | treesnapshot (tar.gz zip) |
| parent | d1ceff405ae476127ec805ae99afa71d095a1bd2 | commitdiff |
target/riscv: Implement AIA IMSIC interface CSRs
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/csr.c | diffblobblamehistory |