| commit | d1ceff405ae476127ec805ae99afa71d095a1bd2 | |
| author | Anup Patel <anup.patel@wdc.com> | |
| Fri, 4 Feb 2022 17:46:50 +0000 (4 23:16 +0530) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 16 Feb 2022 02:24:19 +0000 (16 12:24 +1000) | ||
| tree | 39efc796aad4db301df255e2cdd8bca239c2197a | treesnapshot (tar.gz zip) |
| parent | c7de92b4e829b0df4087371b23e41bbe8aec766d | commitdiff |
target/riscv: Implement AIA xiselect and xireg CSRs
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.h | diffblobblamehistory | |
| target/riscv/csr.c | diffblobblamehistory | |
| target/riscv/machine.c | diffblobblamehistory |