target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
commitb6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 4 Feb 2022 02:26:55 +0000 (4 10:26 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:25:52 +0000 (16 12:25 +1000)
treee921c0f0af88e0e16fe391d4c707cd66893847cc
parent05e6ca5e156d1d114d1eb878cae9744cb4a539e3
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c