target/riscv: add support for svnapot extension
commit2bacb22446a45b07f542d32b6d760da757233b20
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 4 Feb 2022 02:26:56 +0000 (4 10:26 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:25:52 +0000 (16 12:25 +1000)
treec82f0704c3f91cddad65bad7871cbbf424a5308e
parentb6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
target/riscv: add support for svnapot extension

- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c