| commit | aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3 | |
| author | Anup Patel <anup.patel@wdc.com> | |
| Fri, 4 Feb 2022 17:46:43 +0000 (4 23:16 +0530) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 16 Feb 2022 02:24:18 +0000 (16 12:24 +1000) | ||
| tree | 946672d6dc3b1da942a683d37fc883c38f81e793 | treesnapshot (tar.gz zip) |
| parent | 32b0ada038629311aa90499a68de29473df7935d | commitdiff |
target/riscv: Add defines for AIA CSRs
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu_bits.h | diffblobblamehistory |